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Searched refs:x86_pmu (Results 1 – 14 of 14) sorted by relevance

/linux-6.15/arch/x86/events/intel/
H A Dlbr.c194 if (!x86_pmu.lbr_nr) in intel_pmu_lbr_reset()
197 x86_pmu.lbr_reset(); in intel_pmu_lbr_reset()
493 if (i < x86_pmu.lbr_nr) in intel_pmu_arch_lbr_save()
517 x86_pmu.lbr_save(ctx); in __intel_pmu_lbr_save()
572 if (!x86_pmu.lbr_nr) in intel_pmu_lbr_add()
663 if (!x86_pmu.lbr_nr) in intel_pmu_lbr_del()
1162 if (!x86_pmu.lbr_nr) in intel_pmu_setup_lbr_filter()
1400 x86_pmu.lbr_nr = 16; in intel_pmu_lbr_init_snb()
1427 x86_pmu.lbr_nr = 16; in intel_pmu_lbr_init_hsw()
1443 x86_pmu.lbr_nr = 32; in intel_pmu_lbr_init_skl()
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H A Dcore.c3028 if (!x86_pmu.pebs_ept || !x86_pmu.pebs_active || in x86_pmu_handle_guest_pebs()
4357 if (!x86_pmu.pebs) in intel_guest_get_msrs()
4949 if (is_hybrid() || x86_pmu.extra_regs || x86_pmu.lbr_sel_map) { in intel_cpuc_prepare()
5527 x86_pmu.pebs = 0; in intel_clovertown_quirk()
5597 unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr; in is_lbr_from()
6477 x86_pmu.hybrid_pmu = kcalloc(x86_pmu.num_hybrid_pmus, in intel_pmu_init_hybrid()
6624 x86_pmu = core_pmu; in intel_pmu_init()
6636 x86_pmu.pebs_events_mask = intel_pmu_pebs_mask(x86_pmu.cntr_mask64); in intel_pmu_init()
7453 if (x86_pmu.lbr_tos && !check_msr(x86_pmu.lbr_tos, 0x3UL)) in intel_pmu_init()
7454 x86_pmu.lbr_nr = 0; in intel_pmu_init()
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H A Dds.c627 if (!x86_pmu.pebs) in alloc_pebs_buffer()
652 max = x86_pmu.pebs_record_size * (bsiz / x86_pmu.pebs_record_size); in alloc_pebs_buffer()
662 if (!x86_pmu.pebs) in release_pebs_buffer()
682 if (!x86_pmu.bts) in alloc_bts_buffer()
709 if (!x86_pmu.bts) in release_bts_buffer()
737 if (!x86_pmu.bts && !x86_pmu.pebs) in release_ds_buffers()
766 if (!x86_pmu.bts && !x86_pmu.pebs) in reserve_ds_buffers()
769 if (!x86_pmu.bts) in reserve_ds_buffers()
772 if (!x86_pmu.pebs) in reserve_ds_buffers()
2690 if (x86_pmu.pebs) { in intel_ds_init()
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H A Dp6.c203 static __initconst const struct x86_pmu p6_pmu = {
244 x86_pmu.attr_rdpmc_broken = 1; in p6_pmu_rdpmc_quirk()
245 x86_pmu.attr_rdpmc = 0; in p6_pmu_rdpmc_quirk()
251 x86_pmu = p6_pmu; in p6_pmu_init()
H A Dp4.c923 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { in p4_pmu_disable_all()
1002 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { in p4_pmu_enable_all()
1027 wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask); in p4_pmu_set_period()
1044 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { in p4_pmu_handle_irq()
1063 if (!overflow && (val & (1ULL << (x86_pmu.cntval_bits - 1)))) in p4_pmu_handle_irq()
1336 static __initconst const struct x86_pmu p4_pmu = {
1388 x86_pmu = p4_pmu; in p4_pmu_init()
1399 for_each_set_bit(i, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { in p4_pmu_init()
H A Dknc.c290 static const struct x86_pmu knc_pmu __initconst = {
316 x86_pmu = knc_pmu; in knc_pmu_init()
H A Dbts.c602 if (!boot_cpu_has(X86_FEATURE_DTES64) || !x86_pmu.bts) in bts_init()
/linux-6.15/arch/x86/events/
H A Dcore.c49 struct x86_pmu x86_pmu __read_mostly;
556 if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) { in x86_pmu_max_precise()
560 if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2) in x86_pmu_max_precise()
1784 if (x86_pmu.cpu_dead) in x86_pmu_dead_cpu()
1820 x86_pmu.apic = 0; in pmu_check_apic()
2101 if (!check_hw_exists(&pmu, x86_pmu.cntr_mask, x86_pmu.fixed_cntr_mask)) in init_hw_perf_events()
2112 x86_pmu.intel_ctrl = x86_pmu.cntr_mask64; in init_hw_perf_events()
2134 if (!x86_pmu.read) in init_hw_perf_events()
2143 if (!x86_pmu.update) in init_hw_perf_events()
2210 memset(&x86_pmu, 0, sizeof(x86_pmu)); in init_hw_perf_events()
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H A Dperf_event.h748 typeof(&x86_pmu._field) __Fp = &x86_pmu._field; \
768 bool __Fp = x86_pmu._field; \
779 struct x86_pmu { struct
1034 __quirk.next = x86_pmu.quirks; \
1035 x86_pmu.quirks = &__quirk; \
1095 extern struct x86_pmu x86_pmu __read_mostly;
1112 return x86_pmu.lbr_sel_map && in x86_pmu_has_lbr_callstack()
1150 return x86_pmu.eventsel + (x86_pmu.addr_offset ? in x86_pmu_config_addr()
1156 return x86_pmu.perfctr + (x86_pmu.addr_offset ? in x86_pmu_event_addr()
1162 return x86_pmu.fixedctr + (x86_pmu.addr_offset ? in x86_pmu_fixed_ctr_addr()
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/linux-6.15/arch/x86/events/amd/
H A Dcore.c559 if (x86_pmu.lbr_nr) in amd_pmu_cpu_reset()
562 if (x86_pmu.version < 2) in amd_pmu_cpu_reset()
587 if (!x86_pmu.amd_nb_constraints) in amd_pmu_cpu_prepare()
610 if (!x86_pmu.amd_nb_constraints) in amd_pmu_cpu_starting()
934 cnt = min(cnt, x86_pmu.lbr_nr); in amd_pmu_v2_snapshot_branch_stack()
971 if (x86_pmu.lbr_nr) { in amd_pmu_v2_handle_irq()
1306 *left -= x86_pmu.lbr_nr; in amd_pmu_limit_period()
1429 x86_pmu.version = 2; in amd_core_pmu_init()
1473 x86_pmu.flags |= PMU_FL_PAIR; in amd_core_pmu_init()
1523 x86_pmu = amd_pmu; in amd_pmu_init()
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H A Dbrs.c62 x86_pmu.lbr_nr = 16; in amd_brs_detect()
65 x86_pmu.lbr_sel_map = NULL; in amd_brs_detect()
66 x86_pmu.lbr_sel_mask = 0; in amd_brs_detect()
86 if (!x86_pmu.lbr_nr) in amd_brs_setup_filter()
148 if (event->attr.sample_period <= x86_pmu.lbr_nr) in amd_brs_hw_config()
170 return (cfg->msroff ? cfg->msroff : x86_pmu.lbr_nr) - 1; in amd_brs_get_tos()
198 pr_cont("%d-deep BRS, ", x86_pmu.lbr_nr); in amd_brs_init()
302 if (WARN_ON_ONCE(cfg.msroff >= x86_pmu.lbr_nr)) in amd_brs_drain()
H A Dlbr.c170 for (i = 0; i < x86_pmu.lbr_nr; i++) { in amd_pmu_lbr_read()
253 if (!x86_pmu.lbr_nr) in amd_pmu_lbr_setup_filter()
325 if (!x86_pmu.lbr_nr) in amd_pmu_lbr_reset()
329 for (i = 0; i < x86_pmu.lbr_nr; i++) { in amd_pmu_lbr_reset()
344 if (!x86_pmu.lbr_nr) in amd_pmu_lbr_add()
363 if (!x86_pmu.lbr_nr) in amd_pmu_lbr_del()
393 if (!cpuc->lbr_users || !x86_pmu.lbr_nr) in amd_pmu_lbr_enable_all()
415 if (!cpuc->lbr_users || !x86_pmu.lbr_nr) in amd_pmu_lbr_disable_all()
425 if (x86_pmu.version < 2 || !boot_cpu_has(X86_FEATURE_AMD_LBR_V2)) in amd_pmu_lbr_init()
430 x86_pmu.lbr_nr = ebx.split.lbr_v2_stack_sz; in amd_pmu_lbr_init()
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/linux-6.15/arch/x86/events/zhaoxin/
H A Dcore.c370 if (x86_pmu.enabled_ack) in zhaoxin_pmu_handle_irq()
427 if (x86_pmu.event_constraints) { in zhaoxin_get_event_constraints()
529 x86_pmu = zhaoxin_pmu; in zhaoxin_pmu_init()
532 x86_pmu.version = version; in zhaoxin_pmu_init()
536 x86_pmu.events_maskl = ebx.full; in zhaoxin_pmu_init()
552 x86_pmu.max_period = x86_pmu.cntval_mask >> 1; in zhaoxin_pmu_init()
555 x86_pmu.enabled_ack = 1; in zhaoxin_pmu_init()
607 x86_pmu.intel_ctrl = x86_pmu.cntr_mask64; in zhaoxin_pmu_init()
608 x86_pmu.intel_ctrl |= x86_pmu.fixed_cntr_mask64 << INTEL_PMC_IDX_FIXED; in zhaoxin_pmu_init()
610 if (x86_pmu.event_constraints) { in zhaoxin_pmu_init()
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/linux-6.15/arch/x86/xen/
H A Dpmu.c507 if (x86_pmu.handle_irq(&regs)) in xen_pmu_irq_handler()