Searched refs:wrm_reg (Results 1 – 4 of 4) sorted by relevance
966 op_input.wrm_reg.reg0 = reg0; in amdgpu_mes_reg_write_reg_wait()967 op_input.wrm_reg.reg1 = reg1; in amdgpu_mes_reg_write_reg_wait()968 op_input.wrm_reg.ref = ref; in amdgpu_mes_reg_write_reg_wait()969 op_input.wrm_reg.mask = mask; in amdgpu_mes_reg_write_reg_wait()992 op_input.wrm_reg.reg0 = reg; in amdgpu_mes_reg_wait()993 op_input.wrm_reg.ref = val; in amdgpu_mes_reg_wait()994 op_input.wrm_reg.mask = mask; in amdgpu_mes_reg_wait()
624 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; in mes_v11_0_misc_op()625 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; in mes_v11_0_misc_op()626 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; in mes_v11_0_misc_op()632 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; in mes_v11_0_misc_op()633 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; in mes_v11_0_misc_op()634 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; in mes_v11_0_misc_op()635 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; in mes_v11_0_misc_op()
634 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; in mes_v12_0_misc_op()635 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; in mes_v12_0_misc_op()636 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; in mes_v12_0_misc_op()642 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; in mes_v12_0_misc_op()643 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; in mes_v12_0_misc_op()644 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; in mes_v12_0_misc_op()645 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; in mes_v12_0_misc_op()
334 } wrm_reg; member