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Searched refs:wptr_addr (Results 1 – 25 of 26) sorted by relevance

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/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_ih.c70 ih->wptr_addr = dma_addr + ih->ring_size; in amdgpu_ih_ring_init()
97 ih->wptr_addr = adev->wb.gpu_addr + wptr_offs * 4; in amdgpu_ih_ring_init()
133 amdgpu_device_wb_free(adev, (ih->wptr_addr - ih->gpu_addr) / 4); in amdgpu_ih_ring_fini()
H A Damdgpu_mes.h230 uint64_t wptr_addr; member
269 uint64_t wptr_addr; member
302 uint64_t wptr_addr; member
H A Dsi_ih.c84 WREG32(IH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); in si_ih_irq_init()
85 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); in si_ih_irq_init()
H A Dcik_ih.c136 WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); in cik_ih_irq_init()
137 WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); in cik_ih_irq_init()
H A Diceland_ih.c138 WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); in iceland_ih_irq_init()
139 WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); in iceland_ih_irq_init()
H A Dcz_ih.c138 WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); in cz_ih_irq_init()
139 WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); in cz_ih_irq_init()
H A Damdgpu_ih.h62 uint64_t wptr_addr; member
H A Dtonga_ih.c138 WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); in tonga_ih_irq_init()
139 WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); in tonga_ih_irq_init()
H A Dmes_v11_0.c321 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; in mes_v11_0_add_hw_queue()
323 mes_add_queue_pkt.wptr_addr = input->wptr_addr; in mes_v11_0_add_hw_queue()
501 mes_add_queue_pkt.wptr_addr = input->wptr_addr; in mes_v11_0_map_legacy_queue()
781 mes_reset_queue_pkt.wptr_addr_lp = input->wptr_addr; in mes_v11_0_reset_legacy_queue()
H A Dvega10_ih.c237 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); in vega10_ih_enable_ring()
238 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); in vega10_ih_enable_ring()
H A Dnavi10_ih.c293 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); in navi10_ih_enable_ring()
294 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); in navi10_ih_enable_ring()
H A Dvega20_ih.c273 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); in vega20_ih_enable_ring()
274 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); in vega20_ih_enable_ring()
H A Dih_v6_0.c297 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); in ih_v6_0_enable_ring()
298 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); in ih_v6_0_enable_ring()
H A Dih_v6_1.c269 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); in ih_v6_1_enable_ring()
270 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); in ih_v6_1_enable_ring()
H A Dih_v7_0.c269 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); in ih_v7_0_enable_ring()
270 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); in ih_v7_0_enable_ring()
H A Dmes_v12_0.c306 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; in mes_v12_0_add_hw_queue()
522 mes_add_queue_pkt.wptr_addr = input->wptr_addr; in mes_v12_0_map_legacy_queue()
874 mes_reset_queue_pkt.wptr_addr_lp = input->wptr_addr; in mes_v12_0_reset_legacy_queue()
H A Damdgpu_mes.c672 queue_input.wptr_addr = qprops->wptr_gpu_addr; in amdgpu_mes_add_hw_queue()
840 queue_input.wptr_addr = ring->wptr_gpu_addr; in amdgpu_mes_map_legacy_queue()
888 queue_input.wptr_addr = ring->wptr_gpu_addr; in amdgpu_mes_reset_legacy_queue()
H A Dgfx_v9_4_3.c199 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v9_4_3_kiq_map_queues() local
221 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); in gfx_v9_4_3_kiq_map_queues()
222 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); in gfx_v9_4_3_kiq_map_queues()
H A Dgfx_v12_0.c279 uint64_t wptr_addr = ring->wptr_gpu_addr; in gfx_v12_0_kiq_map_queues() local
314 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); in gfx_v12_0_kiq_map_queues()
315 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); in gfx_v12_0_kiq_map_queues()
H A Dgfx_v8_0.c4364 uint64_t wptr_addr = ring->wptr_gpu_addr; in gfx_v8_0_kiq_kcq_enable() local
4378 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); in gfx_v8_0_kiq_kcq_enable()
4379 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); in gfx_v8_0_kiq_kcq_enable()
H A Dgfx_v11_0.c338 uint64_t wptr_addr = ring->wptr_gpu_addr; in gfx11_kiq_map_queues() local
373 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); in gfx11_kiq_map_queues()
374 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); in gfx11_kiq_map_queues()
H A Dgfx_v9_0.c928 uint64_t wptr_addr = ring->wptr_gpu_addr; in gfx_v9_0_kiq_map_queues() local
950 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); in gfx_v9_0_kiq_map_queues()
951 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); in gfx_v9_0_kiq_map_queues()
/linux-6.15/drivers/gpu/drm/amd/include/
H A Dmes_v11_api_def.h291 uint64_t wptr_addr; member
H A Dmes_v12_api_def.h342 uint64_t wptr_addr; member
/linux-6.15/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_device_queue_manager.c229 queue_input.wptr_addr = (uint64_t)q->properties.write_ptr; in add_queue_mes()

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