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Searched refs:wcl_cs_reg (Results 1 – 3 of 3) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_4_3.c3369 uint32_t wcl_cs_reg; in gfx_v9_4_3_emit_wave_limit_cs() local
3376 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS0); in gfx_v9_4_3_emit_wave_limit_cs()
3379 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS1); in gfx_v9_4_3_emit_wave_limit_cs()
3382 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS2); in gfx_v9_4_3_emit_wave_limit_cs()
3385 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS3); in gfx_v9_4_3_emit_wave_limit_cs()
3392 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); in gfx_v9_4_3_emit_wave_limit_cs()
H A Dgfx_v8_0.c6819 uint32_t wcl_cs_reg; in gfx_v8_0_emit_wave_limit_cs() local
6825 wcl_cs_reg = mmSPI_WCL_PIPE_PERCENT_CS0; in gfx_v8_0_emit_wave_limit_cs()
6828 wcl_cs_reg = mmSPI_WCL_PIPE_PERCENT_CS1; in gfx_v8_0_emit_wave_limit_cs()
6831 wcl_cs_reg = mmSPI_WCL_PIPE_PERCENT_CS2; in gfx_v8_0_emit_wave_limit_cs()
6834 wcl_cs_reg = mmSPI_WCL_PIPE_PERCENT_CS3; in gfx_v8_0_emit_wave_limit_cs()
6841 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); in gfx_v8_0_emit_wave_limit_cs()
H A Dgfx_v9_0.c7126 uint32_t wcl_cs_reg; in gfx_v9_0_emit_wave_limit_cs() local
7133 wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS0); in gfx_v9_0_emit_wave_limit_cs()
7136 wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS1); in gfx_v9_0_emit_wave_limit_cs()
7139 wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS2); in gfx_v9_0_emit_wave_limit_cs()
7142 wcl_cs_reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_CS3); in gfx_v9_0_emit_wave_limit_cs()
7149 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); in gfx_v9_0_emit_wave_limit_cs()