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Searched refs:vlv_punit_read (Results 1 – 10 of 10) sorted by relevance

/linux-6.15/drivers/gpu/drm/i915/display/
H A Dintel_display_power_well.c1107 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state) in vlv_set_power_well()
1112 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL); in vlv_set_power_well()
1121 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL)); in vlv_set_power_well()
1156 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask; in vlv_power_well_enabled()
1170 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask; in vlv_power_well_enabled()
1669 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe); in chv_pipe_power_well_enabled()
1682 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSC_MASK(pipe); in chv_pipe_power_well_enabled()
1704 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe)) == state) in chv_set_pipe_power_well()
1709 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); in chv_set_pipe_power_well()
1718 vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM)); in chv_set_pipe_power_well()
H A Di9xx_wm.c112 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); in chv_set_memory_dvfs()
121 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) & in chv_set_memory_dvfs()
135 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); in chv_set_memory_pm5()
3919 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); in vlv_wm_get_hw_state()
3932 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); in vlv_wm_get_hw_state()
3936 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) & in vlv_wm_get_hw_state()
3943 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); in vlv_wm_get_hw_state()
H A Dintel_cdclk.c581 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); in vlv_get_cdclk()
666 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); in vlv_set_cdclk()
670 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & in vlv_set_cdclk()
751 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); in chv_set_cdclk()
755 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & in chv_set_cdclk()
H A Dintel_display_power.c1873 ret = (vlv_punit_read(dev_priv, reg0) & SSPM0_SSC_MASK) == SSPM0_SSC_PWR_GATE; in vlv_punit_is_power_gated()
/linux-6.15/drivers/gpu/drm/xe/compat-i915-headers/
H A Dvlv_sideband.h120 static inline u32 vlv_punit_read(struct drm_i915_private *i915, u32 addr) in vlv_punit_read() function
/linux-6.15/drivers/gpu/drm/i915/
H A Dvlv_sideband.h117 u32 vlv_punit_read(struct drm_i915_private *i915, u32 addr);
H A Dvlv_sideband.c126 u32 vlv_punit_read(struct drm_i915_private *i915, u32 addr) in vlv_punit_read() function
/linux-6.15/drivers/gpu/drm/i915/gt/
H A Dintel_rps.c1285 val = vlv_punit_read(i915, FB_GFX_FMAX_AT_VMAX_FUSE); in chv_rps_max_freq()
1312 val = vlv_punit_read(i915, PUNIT_GPU_DUTYCYCLE_REG); in chv_rps_rpe_freq()
1323 val = vlv_punit_read(i915, FB_GFX_FMAX_AT_VMAX_FUSE); in chv_rps_guar_freq()
1333 val = vlv_punit_read(i915, FB_GFX_FMIN_AT_VMIN_FUSE); in chv_rps_min_freq()
1372 val = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); in chv_rps_enable()
1432 val = vlv_punit_read(i915, PUNIT_REG_GPU_LFM) & 0xff; in vlv_rps_min_freq()
1474 val = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); in vlv_rps_enable()
2125 freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); in __read_cagf()
H A Dintel_gt_pm_debugfs.c370 freq_sts = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); in intel_gt_pm_frequency_dump()
/linux-6.15/drivers/gpu/drm/i915/soc/
H A Dintel_dram.c111 val = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); in vlv_mem_freq()