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Searched refs:vlv (Results 1 – 7 of 7) sorted by relevance

/linux-6.15/drivers/gpu/drm/i915/display/
H A Di9xx_wm.c1720 &crtc_state->wm.vlv.raw[level]; in vlv_raw_plane_wm_is_valid()
1722 &crtc_state->wm.vlv.fifo_state; in vlv_raw_plane_wm_is_valid()
1741 &crtc_state->wm.vlv.fifo_state; in _vlv_compute_pipe_wm()
1836 &crtc_state->wm.vlv.fifo_state; in vlv_compute_pipe_wm()
1863 &crtc_state->wm.vlv.fifo_state; in vlv_atomic_update_fifo()
2105 crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate; in vlv_initial_watermarks()
2121 crtc->wm.active.vlv = crtc_state->wm.vlv.optimal; in vlv_optimize_watermarks()
3956 &crtc_state->wm.vlv.fifo_state; in vlv_wm_get_hw_state()
3968 &crtc_state->wm.vlv.raw[level]; in vlv_wm_get_hw_state()
4043 crtc_state->wm.vlv.optimal; in vlv_wm_sanitize()
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H A Dintel_display_power_map.c204 .vlv.idx = PUNIT_PWGT_IDX_DISP2D,
211 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01),
213 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23),
215 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01),
217 .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23),
223 .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
291 .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
294 .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_D,
H A Dintel_display_power_well.h73 } vlv; member
H A Dintel_display_core.h268 struct vlv_wm_values vlv; member
H A Dintel_display_types.h895 } vlv; member
1399 struct vlv_wm_state vlv; member
H A Dintel_display_power_well.c1095 int pw_idx = i915_power_well_instance(power_well)->vlv.idx; in vlv_set_power_well()
1145 int pw_idx = i915_power_well_instance(power_well)->vlv.idx; in vlv_power_well_enabled()
/linux-6.15/drivers/gpu/drm/i915/
H A Dintel_clock_gating.c725 CG_FUNCS(vlv);