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Searched refs:vgpu_vreg_t (Results 1 – 11 of 11) sorted by relevance

/linux-6.15/drivers/gpu/drm/i915/gvt/
H A Ddisplay.c296 vgpu_vreg_t(vgpu, in emulate_monitor_status_change()
326 vgpu_vreg_t(vgpu, in emulate_monitor_status_change()
357 vgpu_vreg_t(vgpu, in emulate_monitor_status_change()
394 vgpu_vreg_t(vgpu, DPLL_CTRL1) = in emulate_monitor_status_change()
396 vgpu_vreg_t(vgpu, DPLL_CTRL1) |= in emulate_monitor_status_change()
398 vgpu_vreg_t(vgpu, LCPLL1_CTL) = in emulate_monitor_status_change()
415 vgpu_vreg_t(vgpu, DPLL_CTRL2) &= in emulate_monitor_status_change()
417 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= in emulate_monitor_status_change()
419 vgpu_vreg_t(vgpu, DPLL_CTRL2) |= in emulate_monitor_status_change()
441 vgpu_vreg_t(vgpu, DPLL_CTRL2) &= in emulate_monitor_status_change()
[all …]
H A Dmmio.c255 vgpu_vreg_t(vgpu, GEN6_GT_THREAD_STATUS_REG) = 0; in intel_vgpu_reset_mmio()
258 vgpu_vreg_t(vgpu, GEN6_GT_CORE_STATUS) = 0; in intel_vgpu_reset_mmio()
261 vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET; in intel_vgpu_reset_mmio()
264 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &= in intel_vgpu_reset_mmio()
274 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &= in intel_vgpu_reset_mmio()
276 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |= in intel_vgpu_reset_mmio()
279 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &= in intel_vgpu_reset_mmio()
281 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |= in intel_vgpu_reset_mmio()
284 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) &= in intel_vgpu_reset_mmio()
286 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |= in intel_vgpu_reset_mmio()
[all …]
H A Dfb_decoder.c159 u32 stride_reg = vgpu_vreg_t(vgpu, DSPSTRIDE(display, pipe)) & stride_mask; in intel_vgpu_get_stride()
222 val = vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)); in intel_vgpu_decode_primary_plane()
256 plane->base = vgpu_vreg_t(vgpu, DSPSURF(display, pipe)) & I915_GTT_PAGE_MASK; in intel_vgpu_decode_primary_plane()
272 plane->width = (vgpu_vreg_t(vgpu, PIPESRC(display, pipe)) & _PIPE_H_SRCSZ_MASK) >> in intel_vgpu_decode_primary_plane()
275 plane->height = (vgpu_vreg_t(vgpu, PIPESRC(display, pipe)) & in intel_vgpu_decode_primary_plane()
279 val = vgpu_vreg_t(vgpu, DSPTILEOFF(display, pipe)); in intel_vgpu_decode_primary_plane()
354 val = vgpu_vreg_t(vgpu, CURCNTR(display, pipe)); in intel_vgpu_decode_cursor_plane()
380 plane->base = vgpu_vreg_t(vgpu, CURBASE(display, pipe)) & I915_GTT_PAGE_MASK; in intel_vgpu_decode_cursor_plane()
391 val = vgpu_vreg_t(vgpu, CURPOS(display, pipe)); in intel_vgpu_decode_cursor_plane()
397 plane->x_hot = vgpu_vreg_t(vgpu, vgtif_reg(cursor_x_hot)); in intel_vgpu_decode_cursor_plane()
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H A Dvgpu.c44 vgpu_vreg_t(vgpu, vgtif_reg(version_major)) = 1; in populate_pvinfo_page()
45 vgpu_vreg_t(vgpu, vgtif_reg(version_minor)) = 0; in populate_pvinfo_page()
46 vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0; in populate_pvinfo_page()
47 vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id; in populate_pvinfo_page()
49 vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_PPGTT; in populate_pvinfo_page()
51 vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT; in populate_pvinfo_page()
53 vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) = in populate_pvinfo_page()
55 vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.size)) = in populate_pvinfo_page()
57 vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base)) = in populate_pvinfo_page()
64 vgpu_vreg_t(vgpu, vgtif_reg(cursor_x_hot)) = UINT_MAX; in populate_pvinfo_page()
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H A Dedid.c133 vgpu_vreg_t(vgpu, PCH_GMBUS2) = GMBUS_HW_RDY; in reset_gmbus_controller()
135 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER; in reset_gmbus_controller()
167 vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE; in gmbus0_mmio_write()
168 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY | GMBUS_HW_WAIT_PHASE; in gmbus0_mmio_write()
174 vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_SATOER; in gmbus0_mmio_write()
176 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER; in gmbus0_mmio_write()
203 vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_INT; in gmbus1_mmio_write()
204 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY; in gmbus1_mmio_write()
252 vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE; in gmbus1_mmio_write()
264 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_ACTIVE; in gmbus1_mmio_write()
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H A Dmmio_context.c267 *cs++ = vgpu_vreg_t(vgpu, GEN9_GFX_MOCS(index)); in restore_render_mocs_control_for_inhibit()
400 vgpu_vreg_t(vgpu, reg) = 0; in handle_tlb_pending_event()
434 old_v = vgpu_vreg_t(pre, offset); in switch_mocs()
438 new_v = vgpu_vreg_t(next, offset); in switch_mocs()
452 old_v = vgpu_vreg_t(pre, l3_offset); in switch_mocs()
456 new_v = vgpu_vreg_t(next, l3_offset); in switch_mocs()
507 vgpu_vreg_t(pre, mmio->reg) = in switch_mmio()
510 vgpu_vreg_t(pre, mmio->reg) &= in switch_mmio()
512 old_v = vgpu_vreg_t(pre, mmio->reg); in switch_mmio()
531 new_v = vgpu_vreg_t(next, mmio->reg) | in switch_mmio()
[all …]
H A Dhandlers.c355 vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET; in gdrst_mmio_write()
387 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_ON; in pch_pp_control_mmio_write()
393 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= in pch_pp_control_mmio_write()
586 vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 1))); in bxt_vgpu_get_dp_bitrate()
616 dpll_id += (vgpu_vreg_t(vgpu, DPLL_CTRL2) & in skl_vgpu_get_dp_bitrate()
626 switch ((vgpu_vreg_t(vgpu, DPLL_CTRL1) & in skl_vgpu_get_dp_bitrate()
813 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) in ddi_buf_ctl_mmio_write()
833 u32 tx_ctl = vgpu_vreg_t(vgpu, DP_TP_CTL(PORT_E)); in fdi_auto_training_started()
947 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) |= in update_fdi_rx_iir_status()
968 vgpu_vreg_t(vgpu, status_reg) |= (1 << 25); in dp_tp_ctl_mmio_write()
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H A Dcmd_parser.c1401 stride = vgpu_vreg_t(s->vgpu, info->stride_reg) & GENMASK(9, 0); in gen8_check_mi_display_flip()
1402 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & in gen8_check_mi_display_flip()
1405 stride = (vgpu_vreg_t(s->vgpu, info->stride_reg) & in gen8_check_mi_display_flip()
1407 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10; in gen8_check_mi_display_flip()
1427 set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12), in gen8_update_plane_mmio_from_mi_display_flip()
1430 set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(9, 0), in gen8_update_plane_mmio_from_mi_display_flip()
1432 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10), in gen8_update_plane_mmio_from_mi_display_flip()
1435 set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(15, 6), in gen8_update_plane_mmio_from_mi_display_flip()
1437 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(10, 10), in gen8_update_plane_mmio_from_mi_display_flip()
1442 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(display, info->pipe))++; in gen8_update_plane_mmio_from_mi_display_flip()
H A Dscheduler.c653 vgpu_vreg_t(workload->vgpu, RING_START(workload->engine->mmio_base)) = in update_vreg_in_ctx()
972 vgpu_vreg_t(vgpu, RING_TAIL(ring_base)) = tail; in update_guest_context()
973 vgpu_vreg_t(vgpu, RING_HEAD(ring_base)) = head; in update_guest_context()
H A Dgvt.h459 #define vgpu_vreg_t(vgpu, reg) \ macro
H A Dgtt.c991 u32 ips = vgpu_vreg_t(vgpu, GEN8_GAMW_ECO_DEV_RW_IA) & in vgpu_ips_enabled()