Searched refs:vdsc_cfg (Results 1 – 7 of 7) sorted by relevance
114 if (vdsc_cfg->native_420) { in calculate_rc_params()122 vdsc_cfg->nsl_bpg_offset = DIV_ROUND_UP(vdsc_cfg->second_line_bpg_offset << 11, in calculate_rc_params()144 if (vdsc_cfg->native_420) { in calculate_rc_params()246 if (vdsc_cfg->slice_height * vdsc_cfg->slice_width < 15000) in intel_dsc_slice_dimensions_valid()255 if (vdsc_cfg->slice_height * vdsc_cfg->slice_width < 30000) in intel_dsc_slice_dimensions_valid()271 vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width, in intel_dsc_compute_params()303 if (vdsc_cfg->native_420) in intel_dsc_compute_params()348 vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) / in intel_dsc_compute_params()349 (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset); in intel_dsc_compute_params()463 if (vdsc_cfg->simple_422) in intel_dsc_pps_configure()[all …]
1587 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in gen11_dsi_dsc_compute_config() local1606 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; in gen11_dsi_dsc_compute_config()1608 vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay; in gen11_dsi_dsc_compute_config()1615 drm_WARN_ON(display->drm, vdsc_cfg->vbr_enable); in gen11_dsi_dsc_compute_config()1616 drm_WARN_ON(display->drm, vdsc_cfg->simple_422); in gen11_dsi_dsc_compute_config()1618 vdsc_cfg->pic_width % vdsc_cfg->slice_width); in gen11_dsi_dsc_compute_config()1619 drm_WARN_ON(display->drm, vdsc_cfg->slice_height < 8); in gen11_dsi_dsc_compute_config()1621 vdsc_cfg->pic_height % vdsc_cfg->slice_height); in gen11_dsi_dsc_compute_config()1623 ret = drm_dsc_compute_rc_parameters(vdsc_cfg); in gen11_dsi_dsc_compute_config()
1877 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in intel_dp_dsc_compute_params() local1886 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; in intel_dp_dsc_compute_params()1889 vdsc_cfg->slice_height = intel_dp_get_slice_height(vdsc_cfg->pic_height); in intel_dp_dsc_compute_params()1895 vdsc_cfg->dsc_version_major = in intel_dp_dsc_compute_params()1898 vdsc_cfg->dsc_version_minor = in intel_dp_dsc_compute_params()1901 if (vdsc_cfg->convert_rgb) in intel_dp_dsc_compute_params()1902 vdsc_cfg->convert_rgb = in intel_dp_dsc_compute_params()1906 vdsc_cfg->line_buf_depth = min(INTEL_DP_DSC_MAX_LINE_BUF_DEPTH, in intel_dp_dsc_compute_params()1908 if (!vdsc_cfg->line_buf_depth) { in intel_dp_dsc_compute_params()1914 vdsc_cfg->block_pred_enable = in intel_dp_dsc_compute_params()[all …]
3465 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in fill_dsc() local3468 vdsc_cfg->dsc_version_major = dsc->version_major; in fill_dsc()3469 vdsc_cfg->dsc_version_minor = dsc->version_minor; in fill_dsc()3516 vdsc_cfg->rc_model_size = drm_dsc_dp_rc_buffer_size(dsc->rc_buffer_block_size, in fill_dsc()3520 vdsc_cfg->line_buf_depth = VBT_DSC_LINE_BUFFER_DEPTH(dsc->line_buffer_depth); in fill_dsc()3522 vdsc_cfg->block_pred_enable = dsc->block_prediction_enable; in fill_dsc()3524 vdsc_cfg->slice_height = dsc->slice_height; in fill_dsc()
1268 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in psr2_granularity_check() local1300 vdsc_cfg->slice_height % y_granularity) in psr2_granularity_check()2478 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in intel_psr2_sel_fetch_pipe_alignment() local2484 y_alignment = vdsc_cfg->slice_height; in intel_psr2_sel_fetch_pipe_alignment()
1322 if (vdsc_cfg->native_420 || vdsc_cfg->native_422) { in drm_dsc_compute_rc_parameters()1328 vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width / 2 * in drm_dsc_compute_rc_parameters()1337 vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width * in drm_dsc_compute_rc_parameters()1355 slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height; in drm_dsc_compute_rc_parameters()1371 vdsc_cfg->final_offset = vdsc_cfg->rc_model_size - in drm_dsc_compute_rc_parameters()1375 if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) { in drm_dsc_compute_rc_parameters()1381 (vdsc_cfg->rc_model_size - vdsc_cfg->final_offset); in drm_dsc_compute_rc_parameters()1397 vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size - in drm_dsc_compute_rc_parameters()1427 rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset + in drm_dsc_compute_rc_parameters()1433 vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16; in drm_dsc_compute_rc_parameters()[all …]
26 void drm_dsc_set_const_params(struct drm_dsc_config *vdsc_cfg);27 void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);28 int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_type type);29 int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);32 u32 drm_dsc_get_bpp_int(const struct drm_dsc_config *vdsc_cfg);