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Searched refs:vclk_div (Results 1 – 7 of 7) sorted by relevance

/linux-6.15/drivers/gpu/drm/meson/
H A Dmeson_vclk.c375 unsigned int vclk_div; member
387 .vclk_div = 1,
399 .vclk_div = 1,
411 .vclk_div = 1,
423 .vclk_div = 1,
435 .vclk_div = 1,
447 .vclk_div = 2,
459 .vclk_div = 1,
471 .vclk_div = 1,
816 unsigned int vid_pll_div, unsigned int vclk_div, in meson_vclk_set() argument
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/linux-6.15/drivers/gpu/drm/radeon/
H A Dradeon_uvd.c968 unsigned vclk_div, dclk_div, score; in radeon_uvd_calc_upll_dividers() local
979 vclk_div = radeon_uvd_calc_upll_post_div(vco_freq, vclk, in radeon_uvd_calc_upll_dividers()
981 if (vclk_div > pd_max) in radeon_uvd_calc_upll_dividers()
991 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div); in radeon_uvd_calc_upll_dividers()
996 *optimal_vclk_div = vclk_div; in radeon_uvd_calc_upll_dividers()
H A Drv770.c56 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in rv770_set_uvd_clocks() local
76 &fb_div, &vclk_div, &dclk_div); in rv770_set_uvd_clocks()
81 vclk_div -= 1; in rv770_set_uvd_clocks()
104 UPLL_SW_HILEN(vclk_div >> 1) | in rv770_set_uvd_clocks()
105 UPLL_SW_LOLEN((vclk_div >> 1) + (vclk_div & 1)) | in rv770_set_uvd_clocks()
H A Dr600.c205 unsigned fb_div = 0, ref_div, vclk_div = 0, dclk_div = 0; in r600_set_uvd_clocks() local
234 &fb_div, &vclk_div, &dclk_div); in r600_set_uvd_clocks()
261 UPLL_SW_HILEN(vclk_div >> 1) | in r600_set_uvd_clocks()
262 UPLL_SW_LOLEN((vclk_div >> 1) + (vclk_div & 1)) | in r600_set_uvd_clocks()
H A Devergreen.c1192 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in evergreen_set_uvd_clocks() local
1211 &fb_div, &vclk_div, &dclk_div); in evergreen_set_uvd_clocks()
1250 UPLL_PDIV_A(vclk_div) | UPLL_PDIV_B(dclk_div), in evergreen_set_uvd_clocks()
H A Dsi.c6977 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in si_set_uvd_clocks() local
6995 &fb_div, &vclk_div, &dclk_div); in si_set_uvd_clocks()
7036 UPLL_PDIV_A(vclk_div) | UPLL_PDIV_B(dclk_div), in si_set_uvd_clocks()
/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dsi.c1732 unsigned vclk_div, dclk_div, score; in si_calc_upll_dividers() local
1743 vclk_div = si_uvd_calc_upll_post_div(vco_freq, vclk, in si_calc_upll_dividers()
1745 if (vclk_div > pd_max) in si_calc_upll_dividers()
1755 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div); in si_calc_upll_dividers()
1760 *optimal_vclk_div = vclk_div; in si_calc_upll_dividers()
1777 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in si_set_uvd_clocks() local
1795 &fb_div, &vclk_div, &dclk_div); in si_set_uvd_clocks()
1838 UPLL_PDIV_A(vclk_div) | UPLL_PDIV_B(dclk_div), in si_set_uvd_clocks()