Searched refs:v2_1 (Results 1 – 10 of 10) sorted by relevance
522 SET_DCE_CLOCK_PS_ALLOCATION_V2_1 v2_1; member544 args.v2_1.asParam.ulDCEClkFreq = cpu_to_le32(freq); /* 10kHz units */ in amdgpu_atombios_crtc_set_dce_clock()545 args.v2_1.asParam.ucDCEClkType = clk_type; in amdgpu_atombios_crtc_set_dce_clock()546 args.v2_1.asParam.ucDCEClkSrc = clk_src; in amdgpu_atombios_crtc_set_dce_clock()548 ret_freq = le32_to_cpu(args.v2_1.asParam.ulDCEClkFreq) * 10; in amdgpu_atombios_crtc_set_dce_clock()
1565 struct gc_info_v2_1 v2_1; member1652 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v2_1.gc_num_tcp_per_sh); in amdgpu_discovery_get_gfx_info()1653 adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v2_1.gc_tcp_size_per_cu); in amdgpu_discovery_get_gfx_info()1654 …adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v2_1.gc_num_sdp_interface); /* per XC… in amdgpu_discovery_get_gfx_info()1655 adev->gfx.config.gc_num_cu_per_sqc = le32_to_cpu(gc_info->v2_1.gc_num_cu_per_sqc); in amdgpu_discovery_get_gfx_info()1656 …adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_instruction_c… in amdgpu_discovery_get_gfx_info()1657 …adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_scalar_data_cache_si… in amdgpu_discovery_get_gfx_info()1658 adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v2_1.gc_tcc_size); /* per XCD */ in amdgpu_discovery_get_gfx_info()
266 struct rlc_firmware_header_v2_1 v2_1; member
1441 struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1; member1475 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) { in amdgpu_atombios_init_mc_reg_table()1478 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset)); in amdgpu_atombios_init_mc_reg_table()
159 container_of(rlc_hdr_v2_1, struct rlc_firmware_header_v2_2, v2_1); in amdgpu_ucode_print_rlc_hdr()
307 const struct smc_firmware_header_v2_1 *v2_1; in smu_v14_0_set_pptable_v2_1() local312 v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data; in smu_v14_0_set_pptable_v2_1()314 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset)); in smu_v14_0_set_pptable_v2_1()315 pptable_count = le32_to_cpu(v2_1->pptable_count); in smu_v14_0_set_pptable_v2_1()318 *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes)); in smu_v14_0_set_pptable_v2_1()
290 const struct smc_firmware_header_v2_1 *v2_1; in smu_v11_0_set_pptable_v2_1() local295 v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data; in smu_v11_0_set_pptable_v2_1()297 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset)); in smu_v11_0_set_pptable_v2_1()298 pptable_count = le32_to_cpu(v2_1->pptable_count); in smu_v11_0_set_pptable_v2_1()301 *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes)); in smu_v11_0_set_pptable_v2_1()
315 const struct smc_firmware_header_v2_1 *v2_1; in smu_v13_0_set_pptable_v2_1() local320 v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data; in smu_v13_0_set_pptable_v2_1()322 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset)); in smu_v13_0_set_pptable_v2_1()323 pptable_count = le32_to_cpu(v2_1->pptable_count); in smu_v13_0_set_pptable_v2_1()326 *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes)); in smu_v13_0_set_pptable_v2_1()
438 const struct smc_firmware_header_v2_1 *v2_1; in smu_v13_0_6_init_microcode() local472 v2_1 = (const struct smc_firmware_header_v2_1 *)adev->pm.fw->data; in smu_v13_0_6_init_microcode()474 *)((uint8_t *)v2_1 + in smu_v13_0_6_init_microcode()475 le32_to_cpu(v2_1->pptable_entry_offset)); in smu_v13_0_6_init_microcode()476 p2stable_count = le32_to_cpu(v2_1->pptable_count); in smu_v13_0_6_init_microcode()480 ((uint8_t *)v2_1 + in smu_v13_0_6_init_microcode()
3818 struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1; member3881 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) { in radeon_atom_get_memory_info()3883 (ATOM_VRAM_MODULE_V7 *)vram_info->v2_1.aVramInfo; in radeon_atom_get_memory_info()4006 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) { in radeon_atom_init_mc_reg_table()4009 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset)); in radeon_atom_init_mc_reg_table()