| /linux-6.15/drivers/gpu/drm/amd/amdkfd/ |
| H A D | kfd_packet_manager_v9.c | 79 packet->gds_addr_hi = upper_32_bits(qpd->gds_context_area); in pm_map_process_v9()
84 upper_32_bits(vm_page_table_base_addr); in pm_map_process_v9()
137 packet->gds_addr_hi = upper_32_bits(qpd->gds_context_area); in pm_map_process_aldebaran()
142 upper_32_bits(vm_page_table_base_addr); in pm_map_process_aldebaran()
185 packet->ib_base_hi = upper_32_bits(ib); in pm_runlist_v9()
210 packet->gws_mask_hi = upper_32_bits(res->gws_mask); in pm_set_resources_v9()
213 packet->queue_mask_hi = upper_32_bits(res->queue_mask); in pm_set_resources_v9()
289 upper_32_bits(q->gart_mqd_addr); in pm_map_queues_v9()
295 upper_32_bits((uint64_t)q->properties.write_ptr); in pm_map_queues_v9()
460 packet->addr_hi = upper_32_bits((uint64_t)fence_address); in pm_query_status_v9()
[all …]
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| H A D | kfd_packet_manager_vi.c | 71 packet->gds_addr_hi = upper_32_bits(qpd->gds_context_area); in pm_map_process_vi()
110 packet->bitfields3.ib_base_hi = upper_32_bits(ib); in pm_runlist_vi()
135 packet->gws_mask_hi = upper_32_bits(res->gws_mask); in pm_set_resources_vi()
138 packet->queue_mask_hi = upper_32_bits(res->queue_mask); in pm_set_resources_vi()
190 upper_32_bits(q->gart_mqd_addr); in pm_map_queues_vi()
196 upper_32_bits((uint64_t)q->properties.write_ptr); in pm_map_queues_vi()
264 packet->addr_hi = upper_32_bits((uint64_t)fence_address); in pm_query_status_vi()
266 packet->data_hi = upper_32_bits((uint64_t)fence_value); in pm_query_status_vi()
294 packet->address_hi = upper_32_bits(gpu_addr); in pm_release_mem_vi()
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| H A D | kfd_mqd_manager_v12.c | 129 m->cp_mqd_base_addr_hi = upper_32_bits(addr); in init_mqd()
154 upper_32_bits(q->ctx_save_restore_area_address); in init_mqd()
195 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); in update_mqd()
198 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); in update_mqd()
200 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); in update_mqd()
222 upper_32_bits(q->eop_ring_buffer_address >> 8); in update_mqd()
337 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); in update_mqd_sdma()
339 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
341 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); in update_mqd_sdma()
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| H A D | kfd_mqd_manager_vi.c | 117 m->cp_mqd_base_addr_hi = upper_32_bits(addr); in init_mqd()
131 m->compute_tba_hi = upper_32_bits(q->tba_addr >> 8); in init_mqd()
133 m->compute_tma_hi = upper_32_bits(q->tma_addr >> 8); in init_mqd()
144 upper_32_bits(q->ctx_save_restore_area_address); in init_mqd()
185 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); in __update_mqd()
188 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); in __update_mqd()
190 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); in __update_mqd()
217 upper_32_bits(q->eop_ring_buffer_address >> 8); in __update_mqd()
371 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); in update_mqd_sdma()
373 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
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| /linux-6.15/drivers/gpu/drm/radeon/ |
| H A D | si_dma.c | 82 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; in si_dma_vm_copy_pages()
83 ib->ptr[ib->length_dw++] = upper_32_bits(src) & 0xff; in si_dma_vm_copy_pages()
121 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; in si_dma_vm_write_pages()
133 ib->ptr[ib->length_dw++] = upper_32_bits(value); in si_dma_vm_write_pages()
173 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; in si_dma_vm_set_pages()
177 ib->ptr[ib->length_dw++] = upper_32_bits(value); in si_dma_vm_set_pages()
265 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); in si_copy_dma()
266 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff); in si_copy_dma()
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| H A D | evergreen_dma.c | 48 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff)); in evergreen_dma_fence_ring_emit()
78 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff); in evergreen_dma_ring_ib_execute()
89 radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); in evergreen_dma_ring_ib_execute()
142 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); in evergreen_copy_dma()
143 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff); in evergreen_copy_dma()
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| H A D | r600_dma.c | 143 upper_32_bits(rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFF); in r600_dma_resume()
255 radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xff); in r600_dma_ring_test()
295 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff)); in r600_dma_fence_ring_emit()
322 radeon_ring_write(ring, upper_32_bits(addr) & 0xff); in r600_dma_semaphore_ring_emit()
360 ib.ptr[2] = upper_32_bits(gpu_addr) & 0xff; in r600_dma_ib_test()
415 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff); in r600_dma_ring_ib_execute()
426 radeon_ring_write(ring, (ib->length_dw << 16) | (upper_32_bits(ib->gpu_addr) & 0xFF)); in r600_dma_ring_ib_execute()
478 radeon_ring_write(ring, (((upper_32_bits(dst_offset) & 0xff) << 16) | in r600_copy_dma()
479 (upper_32_bits(src_offset) & 0xff))); in r600_copy_dma()
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| H A D | ni_dma.c | 134 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff); in cayman_dma_ring_ib_execute()
145 radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); in cayman_dma_ring_ib_execute()
222 upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFF); in cayman_dma_resume()
330 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; in cayman_dma_vm_copy_pages()
331 ib->ptr[ib->length_dw++] = upper_32_bits(src) & 0xff; in cayman_dma_vm_copy_pages()
370 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; in cayman_dma_vm_write_pages()
382 ib->ptr[ib->length_dw++] = upper_32_bits(value); in cayman_dma_vm_write_pages()
422 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; in cayman_dma_vm_set_pages()
426 ib->ptr[ib->length_dw++] = upper_32_bits(value); in cayman_dma_vm_set_pages()
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| H A D | cik_sdma.c | 155 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr)); in cik_sdma_ring_ib_execute()
208 radeon_ring_write(ring, upper_32_bits(addr)); in cik_sdma_fence_ring_emit()
237 radeon_ring_write(ring, upper_32_bits(addr)); in cik_sdma_semaphore_ring_emit()
670 radeon_ring_write(ring, upper_32_bits(gpu_addr)); in cik_sdma_ring_test()
728 ib.ptr[2] = upper_32_bits(gpu_addr); in cik_sdma_ib_test()
817 ib->ptr[ib->length_dw++] = upper_32_bits(src); in cik_sdma_vm_copy_pages()
819 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in cik_sdma_vm_copy_pages()
858 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in cik_sdma_vm_write_pages()
871 ib->ptr[ib->length_dw++] = upper_32_bits(value); in cik_sdma_vm_write_pages()
911 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in cik_sdma_vm_set_pages()
[all …]
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| /linux-6.15/drivers/gpu/drm/amd/amdgpu/ |
| H A D | si_dma.c | 99 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xff)); in si_dma_ring_emit_fence()
106 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xff)); in si_dma_ring_emit_fence()
107 amdgpu_ring_write(ring, upper_32_bits(seq)); in si_dma_ring_emit_fence()
268 ib.ptr[2] = upper_32_bits(gpu_addr) & 0xff; in si_dma_ring_test_ib()
316 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; in si_dma_vm_copy_pte()
317 ib->ptr[ib->length_dw++] = upper_32_bits(src) & 0xff; in si_dma_vm_copy_pte()
339 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in si_dma_vm_write_pte()
342 ib->ptr[ib->length_dw++] = upper_32_bits(value); in si_dma_vm_write_pte()
380 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; in si_dma_vm_set_pte_pde()
382 ib->ptr[ib->length_dw++] = upper_32_bits(flags); in si_dma_vm_set_pte_pde()
[all …]
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| H A D | sdma_v7_0.c | 149 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v7_0_ring_init_cond_exec()
243 upper_32_bits(ring->wptr << 2)); in sdma_v7_0_ring_set_wptr()
257 upper_32_bits(ring->wptr << 2)); in sdma_v7_0_ring_set_wptr()
265 upper_32_bits(ring->wptr << 2)); in sdma_v7_0_ring_set_wptr()
394 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v7_0_ring_emit_fence()
405 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v7_0_ring_emit_fence()
406 amdgpu_ring_write(ring, upper_32_bits(seq)); in sdma_v7_0_ring_emit_fence()
544 upper_32_bits(wptr_gpu_addr)); in sdma_v7_0_gfx_resume_instance()
1078 ib.ptr[2] = upper_32_bits(gpu_addr); in sdma_v7_0_ring_test_ib()
1145 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in sdma_v7_0_vm_copy_pte()
[all …]
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| H A D | sdma_v6_0.c | 149 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v6_0_ring_init_cond_exec()
215 upper_32_bits(ring->wptr << 2)); in sdma_v6_0_ring_set_wptr()
229 upper_32_bits(ring->wptr << 2)); in sdma_v6_0_ring_set_wptr()
235 upper_32_bits(ring->wptr << 2)); in sdma_v6_0_ring_set_wptr()
363 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v6_0_ring_emit_fence()
374 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v6_0_ring_emit_fence()
375 amdgpu_ring_write(ring, upper_32_bits(seq)); in sdma_v6_0_ring_emit_fence()
525 upper_32_bits(wptr_gpu_addr)); in sdma_v6_0_gfx_resume_instance()
1034 ib.ptr[2] = upper_32_bits(gpu_addr); in sdma_v6_0_ring_test_ib()
1099 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in sdma_v6_0_vm_copy_pte()
[all …]
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| H A D | sdma_v5_2.c | 148 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v5_2_ring_init_cond_exec()
221 upper_32_bits(ring->wptr << 2)); in sdma_v5_2_ring_set_wptr()
236 upper_32_bits(ring->wptr << 2)); in sdma_v5_2_ring_set_wptr()
245 upper_32_bits(ring->wptr << 2)); in sdma_v5_2_ring_set_wptr()
249 upper_32_bits(ring->wptr << 2)); in sdma_v5_2_ring_set_wptr()
381 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v5_2_ring_emit_fence()
392 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v5_2_ring_emit_fence()
393 amdgpu_ring_write(ring, upper_32_bits(seq)); in sdma_v5_2_ring_emit_fence()
580 upper_32_bits(wptr_gpu_addr)); in sdma_v5_2_gfx_resume_instance()
1020 ib.ptr[2] = upper_32_bits(gpu_addr); in sdma_v5_2_ring_test_ib()
[all …]
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| H A D | sdma_v2_4.c | 314 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v2_4_ring_emit_fence()
322 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v2_4_ring_emit_fence()
323 amdgpu_ring_write(ring, upper_32_bits(seq)); in sdma_v2_4_ring_emit_fence()
555 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); in sdma_v2_4_ring_test_ring()
610 ib.ptr[2] = upper_32_bits(gpu_addr); in sdma_v2_4_ring_test_ib()
664 ib->ptr[ib->length_dw++] = upper_32_bits(src); in sdma_v2_4_vm_copy_pte()
666 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in sdma_v2_4_vm_copy_pte()
689 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in sdma_v2_4_vm_write_pte()
717 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in sdma_v2_4_vm_set_pte_pde()
719 ib->ptr[ib->length_dw++] = upper_32_bits(flags); in sdma_v2_4_vm_set_pte_pde()
[all …]
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| H A D | amdgpu_cper.c | 298 reg_data.status_hi = upper_32_bits(bank->regs[ACA_REG_IDX_STATUS]); in amdgpu_cper_generate_ue_record()
300 reg_data.addr_hi = upper_32_bits(bank->regs[ACA_REG_IDX_ADDR]); in amdgpu_cper_generate_ue_record()
302 reg_data.ipid_hi = upper_32_bits(bank->regs[ACA_REG_IDX_IPID]); in amdgpu_cper_generate_ue_record()
304 reg_data.synd_hi = upper_32_bits(bank->regs[ACA_REG_IDX_SYND]); in amdgpu_cper_generate_ue_record()
390 reg_data[CPER_ACA_REG_CTL_HI] = upper_32_bits(bank->regs[ACA_REG_IDX_CTL]); in amdgpu_cper_generate_ce_records()
392 reg_data[CPER_ACA_REG_STATUS_HI] = upper_32_bits(bank->regs[ACA_REG_IDX_STATUS]); in amdgpu_cper_generate_ce_records()
394 reg_data[CPER_ACA_REG_ADDR_HI] = upper_32_bits(bank->regs[ACA_REG_IDX_ADDR]); in amdgpu_cper_generate_ce_records()
396 reg_data[CPER_ACA_REG_MISC0_HI] = upper_32_bits(bank->regs[ACA_REG_IDX_MISC0]); in amdgpu_cper_generate_ce_records()
398 reg_data[CPER_ACA_REG_CONFIG_HI] = upper_32_bits(bank->regs[ACA_REG_IDX_CONFIG]); in amdgpu_cper_generate_ce_records()
400 reg_data[CPER_ACA_REG_IPID_HI] = upper_32_bits(bank->regs[ACA_REG_IDX_IPID]); in amdgpu_cper_generate_ce_records()
[all …]
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| H A D | cik_sdma.c | 286 amdgpu_ring_write(ring, upper_32_bits(addr)); in cik_sdma_ring_emit_fence()
294 amdgpu_ring_write(ring, upper_32_bits(addr)); in cik_sdma_ring_emit_fence()
295 amdgpu_ring_write(ring, upper_32_bits(seq)); in cik_sdma_ring_emit_fence()
624 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); in cik_sdma_ring_test_ring()
679 ib.ptr[2] = upper_32_bits(gpu_addr); in cik_sdma_ring_test_ib()
729 ib->ptr[ib->length_dw++] = upper_32_bits(src); in cik_sdma_vm_copy_pte()
731 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in cik_sdma_vm_copy_pte()
754 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in cik_sdma_vm_write_pte()
782 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in cik_sdma_vm_set_pte_pde()
784 ib->ptr[ib->length_dw++] = upper_32_bits(flags); in cik_sdma_vm_set_pte_pde()
[all …]
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| H A D | sdma_v5_0.c | 308 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v5_0_ring_init_cond_exec()
411 upper_32_bits(ring->wptr << 2)); in sdma_v5_0_ring_set_wptr()
425 upper_32_bits(ring->wptr << 2)); in sdma_v5_0_ring_set_wptr()
431 upper_32_bits(ring->wptr << 2)); in sdma_v5_0_ring_set_wptr()
562 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v5_0_ring_emit_fence()
574 amdgpu_ring_write(ring, upper_32_bits(seq)); in sdma_v5_0_ring_emit_fence()
761 upper_32_bits(wptr_gpu_addr)); in sdma_v5_0_gfx_resume_instance()
793 upper_32_bits(ring->wptr << 2)); in sdma_v5_0_gfx_resume_instance()
1164 ib.ptr[2] = upper_32_bits(gpu_addr); in sdma_v5_0_ring_test_ib()
1229 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in sdma_v5_0_vm_copy_pte()
[all …]
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| /linux-6.15/drivers/pci/controller/mobiveil/ |
| H A D | pcie-mobiveil.c | 154 mobiveil_csr_writel(pcie, upper_32_bits(size64), in program_ib_windows()
159 mobiveil_csr_writel(pcie, upper_32_bits(cpu_addr), in program_ib_windows()
164 mobiveil_csr_writel(pcie, upper_32_bits(pci_addr), in program_ib_windows()
195 mobiveil_csr_writel(pcie, upper_32_bits(size64), in program_ob_windows()
205 mobiveil_csr_writel(pcie, upper_32_bits(cpu_addr), in program_ob_windows()
210 mobiveil_csr_writel(pcie, upper_32_bits(pci_addr), in program_ob_windows()
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| /linux-6.15/drivers/iio/test/ |
| H A D | iio-test-format.c | 212 values[1] = upper_32_bits(value); in iio_test_iio_format_value_integer_64()
218 values[1] = upper_32_bits(value); in iio_test_iio_format_value_integer_64()
224 values[1] = upper_32_bits(value); in iio_test_iio_format_value_integer_64()
230 values[1] = upper_32_bits(value); in iio_test_iio_format_value_integer_64()
236 values[1] = upper_32_bits(value); in iio_test_iio_format_value_integer_64()
242 values[1] = upper_32_bits(value); in iio_test_iio_format_value_integer_64()
248 values[1] = upper_32_bits(value); in iio_test_iio_format_value_integer_64()
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| /linux-6.15/drivers/pci/controller/ |
| H A D | pci-xgene.c | 299 val = (val32 & 0x0000ffff) | (upper_32_bits(mask) << 16); in xgene_pcie_set_ib_mask()
303 val = (val32 & 0xffff0000) | (upper_32_bits(mask) >> 16); in xgene_pcie_set_ib_mask()
389 xgene_pcie_writel(port, offset + 0x04, upper_32_bits(cpu_addr)); in xgene_pcie_setup_ob_reg()
391 xgene_pcie_writel(port, offset + 0x0c, upper_32_bits(mask)); in xgene_pcie_setup_ob_reg()
393 xgene_pcie_writel(port, offset + 0x14, upper_32_bits(pci_addr)); in xgene_pcie_setup_ob_reg()
401 xgene_pcie_writel(port, CFGBARH, upper_32_bits(addr)); in xgene_pcie_setup_cfg_reg()
451 upper_32_bits(pim) | EN_COHERENCY); in xgene_pcie_setup_pims()
453 xgene_pcie_writel(port, pim_reg + 0x14, upper_32_bits(size)); in xgene_pcie_setup_pims()
510 writel(upper_32_bits(cpu_addr), bar_addr + 0x4); in xgene_pcie_setup_ib_reg()
520 xgene_pcie_writel(port, IBAR3L + 0x4, upper_32_bits(cpu_addr)); in xgene_pcie_setup_ib_reg()
[all …]
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| /linux-6.15/drivers/net/ethernet/apm/xgene-v2/ |
| H A D | ring.c | 28 dma_h = upper_32_bits(next_dma); in xge_setup_desc()
40 xge_wr_csr(pdata, DMATXDESCH, upper_32_bits(dma_addr)); in xge_update_tx_desc_addr()
52 xge_wr_csr(pdata, DMARXDESCH, upper_32_bits(dma_addr)); in xge_update_rx_desc_addr()
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| /linux-6.15/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/ |
| H A D | gm20b.c | 74 hdr.code_dma_base1 = upper_32_bits((addr + adjust) >> 8); in gm20b_pmu_acr_bld_patch()
77 hdr.data_dma_base1 = upper_32_bits((addr + adjust) >> 8); in gm20b_pmu_acr_bld_patch()
80 hdr.overlay_dma_base1 = upper_32_bits((addr + adjust) << 8); in gm20b_pmu_acr_bld_patch()
104 .code_dma_base1 = upper_32_bits(code), in gm20b_pmu_acr_bld_write()
105 .data_dma_base1 = upper_32_bits(data), in gm20b_pmu_acr_bld_write()
106 .overlay_dma_base1 = upper_32_bits(code), in gm20b_pmu_acr_bld_write()
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| /linux-6.15/drivers/gpu/drm/nouveau/nvkm/engine/fifo/ |
| H A D | gv100.c | 48 nvkm_wo32(chan->inst, 0x00c, upper_32_bits(userd)); in gv100_chan_ramfc_write()
52 nvkm_wo32(chan->inst, 0x04c, upper_32_bits(offset) | (limit2 << 16)); in gv100_chan_ramfc_write()
103 nvkm_wo32(chan->inst, 0x214, upper_32_bits(addr)); in gv100_ectx_bind()
123 nvkm_wo32(chan->inst, 0x224, upper_32_bits(bar2)); in gv100_ectx_ce_bind()
189 nvkm_wo32(memory, offset + 0x4, upper_32_bits(user)); in gv100_runl_insert_chan()
191 nvkm_wo32(memory, offset + 0xc, upper_32_bits(inst)); in gv100_runl_insert_chan()
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| /linux-6.15/drivers/gpu/drm/nouveau/nvkm/engine/gr/ |
| H A D | gm20b.c | 42 hdr.code_dma_base1 = upper_32_bits((addr + adjust) >> 8); in gm20b_gr_acr_bld_patch()
45 hdr.data_dma_base1 = upper_32_bits((addr + adjust) >> 8); in gm20b_gr_acr_bld_patch()
66 .code_dma_base1 = upper_32_bits(code), in gm20b_gr_acr_bld_write()
67 .data_dma_base1 = upper_32_bits(data), in gm20b_gr_acr_bld_write()
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| /linux-6.15/drivers/media/pci/pt3/ |
| H A D | pt3_dma.c | 54 iowrite32(upper_32_bits(adap->desc_buf[0].b_addr), in pt3_start_dma()
185 d->next_h = upper_32_bits(desc_addr); in pt3_alloc_dmabuf()
191 d->addr_h = upper_32_bits(data_addr); in pt3_alloc_dmabuf()
196 d->next_h = upper_32_bits(desc_addr); in pt3_alloc_dmabuf()
205 d->next_h = upper_32_bits(desc_addr); in pt3_alloc_dmabuf()
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