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Searched refs:ufshcd_rmwl (Results 1 – 6 of 6) sorted by relevance

/linux-6.15/drivers/ufs/host/
H A Dufs-qcom.h206 ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, UFS_PHY_SOFT_RESET, REG_UFS_CFG1); in ufs_qcom_assert_reset()
217 ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, 0, REG_UFS_CFG1); in ufs_qcom_deassert_reset()
H A Dufs-qcom.c367 ufshcd_rmwl(host->hba, QUNIPRO_SEL, QUNIPRO_SEL, REG_UFS_CFG1); in ufs_qcom_select_unipro_mode()
370 ufshcd_rmwl(host->hba, QUNIPRO_G4_SEL, 0, REG_UFS_CFG0); in ufs_qcom_select_unipro_mode()
500 ufshcd_rmwl(hba, REG_UFS_CFG2_CGC_EN_ALL, REG_UFS_CFG2_CGC_EN_ALL, in ufs_qcom_enable_hw_clk_gating()
1508 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN, in ufs_qcom_enable_test_bus()
1510 ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1); in ufs_qcom_enable_test_bus()
1601 ufshcd_rmwl(host->hba, TEST_BUS_SEL, in ufs_qcom_testbus_config()
1604 ufshcd_rmwl(host->hba, mask, in ufs_qcom_testbus_config()
1639 ufshcd_rmwl(hba, UTP_DBG_RAMS_EN, 0, REG_UFS_CFG1); in ufs_qcom_dump_dbg_regs()
1915 ufshcd_rmwl(hba, ESI_VEC_MASK, in ufs_qcom_config_esi()
H A Dufs-mediatek.c1762 ufshcd_rmwl(hba, MCQ_INTR_EN_MSK, 0, REG_UFS_MMIO_OPT_CTRL_0); in ufs_mtk_config_mcq()
1773 ufshcd_rmwl(hba, MCQ_AH8, MCQ_AH8, REG_UFS_MMIO_OPT_CTRL_0); in ufs_mtk_config_mcq()
1774 ufshcd_rmwl(hba, MCQ_INTR_EN_MSK, MCQ_MULTI_INTR_EN, REG_UFS_MMIO_OPT_CTRL_0); in ufs_mtk_config_mcq()
H A Dufs-exynos.c252 ufshcd_rmwl(hba, MHCTRL_EN_VH_MASK, MHCTRL_EN_VH(1), MHCTRL); in exynosauto_ufs_post_hce_enable()
/linux-6.15/drivers/ufs/core/
H A Dufs-mcq.c422 ufshcd_rmwl(hba, MCQ_MODE_SELECT, MCQ_MODE_SELECT, REG_UFS_MEM_CFG); in ufshcd_mcq_enable()
429 ufshcd_rmwl(hba, MCQ_MODE_SELECT, 0, REG_UFS_MEM_CFG); in ufshcd_mcq_disable()
/linux-6.15/include/ufs/
H A Dufshcd.h1312 static inline void ufshcd_rmwl(struct ufs_hba *hba, u32 mask, u32 val, u32 reg) in ufshcd_rmwl() function