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Searched refs:ufshcd_readl (Results 1 – 15 of 15) sorted by relevance

/linux-6.15/drivers/ufs/host/
H A Dufs-qcom.h197 u32 ver = ufshcd_readl(hba, REG_UFS_HW_VERSION); in ufs_qcom_get_controller_revision()
212 ufshcd_readl(hba, REG_UFS_CFG1); in ufs_qcom_assert_reset()
223 ufshcd_readl(hba, REG_UFS_CFG1); in ufs_qcom_deassert_reset()
H A Dcdns-pltfrm.c139 ufshcd_readl(hba, CDNS_UFS_REG_HCLKDIV); in cdns_ufs_set_hclkdiv()
240 data = ufshcd_readl(hba, CDNS_UFS_REG_PHY_XCFGD1); in cdns_ufs_m31_16nm_phy_initialization()
H A Dufs-qcom.c167 caps.reg_val = cpu_to_le32(ufshcd_readl(hba, REG_UFS_CCAP)); in ufs_qcom_ice_init()
186 cap.reg_val = cpu_to_le32(ufshcd_readl(hba, in ufs_qcom_ice_init()
422 return UFS_QCOM_MAX_GEAR(ufshcd_readl(hba, REG_UFS_PARAM0)); in ufs_qcom_get_hs_gear()
504 ufshcd_readl(hba, REG_UFS_CFG2); in ufs_qcom_enable_hw_clk_gating()
580 if (ufshcd_readl(hba, REG_UFS_SYS1CLK_1US) != core_clk_cycles_per_us) { in ufs_qcom_cfg_timers()
586 ufshcd_readl(hba, REG_UFS_SYS1CLK_1US); in ufs_qcom_cfg_timers()
1019 val = ufshcd_readl(host->hba, REG_UFS_DEBUG_SPARE_CFG); in ufs_qcom_set_phy_gear()
1625 reg = ufshcd_readl(hba, REG_UFS_CFG1); in ufs_qcom_dump_dbg_regs()
H A Dufs-sprd.c53 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE); in ufs_sprd_ctrl_uic_compl()
228 val = ufshcd_readl(hba, REG_CONTROLLER_ENABLE); in ufs_sprd_n6_key_acc_enable()
H A Dufs-mediatek.c268 ufshcd_readl(hba, REG_UFS_XOUFS_CTRL) | 0x80, in ufs_mtk_hce_enable_notify()
336 value = ufshcd_readl(hba, REG_UFS_REFCLK_CTRL); in ufs_mtk_setup_ref_clk()
408 val = ufshcd_readl(hba, REG_UFS_PROBE); in ufs_mtk_wait_idle_state()
441 val = ufshcd_readl(hba, REG_UFS_PROBE); in ufs_mtk_wait_link_state()
1053 host->ip_ver = ufshcd_readl(hba, REG_UFS_MTK_IP_VER); in ufs_mtk_init()
1330 (ufshcd_readl(hba, REG_UFS_XOUFS_CTRL) & ~0x100), in ufs_mtk_link_set_lpm()
H A Dufs-hisi.c235 reg = ufshcd_readl(hba, REG_AUTO_HIBERNATE_IDLE_TIMER); in ufs_hisi_link_startup_pre_change()
H A Dufs-renesas.c57 return ufshcd_readl(hba, reg); in ufs_renesas_read()
H A Dufs-exynos.c334 enabled_vh = ufshcd_readl(hba, MHCTRL) & MHCTRL_EN_VH_MASK; in exynosauto_ufs_post_pwr_change()
1296 if (!(ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES) & in exynos_ufs_fmp_init()
1759 mbox = ufshcd_readl(hba, PH2VH_MBOX); in exynosauto_ufs_vh_wait_ph_ready()
H A Dufshcd-pci.c105 u32 hce = ufshcd_readl(hba, REG_CONTROLLER_ENABLE); in ufs_intel_hce_enable_notify()
/linux-6.15/drivers/ufs/core/
H A Dufshcd-crypto.c167 cpu_to_le32(ufshcd_readl(hba, REG_UFS_CCAP)); in ufshcd_hba_init_crypto_capabilities()
198 cpu_to_le32(ufshcd_readl(hba, in ufshcd_hba_init_crypto_capabilities()
H A Dufshcd.c173 regs[pos / 4] = ufshcd_readl(hba, offset + pos); in ufshcd_dump_regs()
420 cmd = ufshcd_readl(hba, REG_UIC_COMMAND); in ufshcd_add_uic_command_trace()
423 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_1), in ufshcd_add_uic_command_trace()
424 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2), in ufshcd_add_uic_command_trace()
425 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3)); in ufshcd_add_uic_command_trace()
468 intr = ufshcd_readl(hba, REG_INTERRUPT_STATUS); in ufshcd_add_command_trace()
775 ufshci_ver = ufshcd_readl(hba, REG_UFS_VERSION); in ufshcd_get_ufs_version()
877 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) & in ufshcd_get_uic_cmd_result()
891 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3); in ufshcd_get_dme_attr_val()
4274 ufshcd_readl(hba, REG_INTERRUPT_ENABLE); in ufshcd_uic_pwr_ctrl()
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H A Dufs-mcq.c95 val = ufshcd_readl(hba, REG_UFS_MCQ_CFG); in ufshcd_mcq_config_mac()
154 ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES); in ufshcd_mcq_decide_queue_depth()
435 ufshcd_writel(hba, ufshcd_readl(hba, REG_UFS_MEM_CFG) | 0x2, in ufshcd_mcq_enable_esi()
H A Dufshcd-priv.h118 return ufshcd_readl(hba, REG_UFS_VERSION); in ufshcd_vops_get_ufs_hci_version()
H A Dufs-sysfs.c211 *val = ufshcd_readl(hba, reg); in ufshcd_read_hci_reg()
/linux-6.15/include/ufs/
H A Dufshcd.h1302 #define ufshcd_readl(hba, reg) \ macro
1316 tmp = ufshcd_readl(hba, reg); in ufshcd_rmwl()