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Searched refs:ufshcd_dme_set (Results 1 – 11 of 11) sorted by relevance

/linux-6.15/drivers/ufs/host/
H A Dufs-hisi.c257 ufshcd_dme_set(hba, UIC_ARG_MIB(0x2044), 0x0); in ufs_hisi_link_startup_post_change()
259 ufshcd_dme_set(hba, UIC_ARG_MIB(0x2045), 0x0); in ufs_hisi_link_startup_post_change()
261 ufshcd_dme_set(hba, UIC_ARG_MIB(0x2040), 0x9); in ufs_hisi_link_startup_post_change()
319 ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0x15a7), 0xA); in ufs_hisi_pwr_change_pre_change()
321 ufshcd_dme_set(hba, UIC_ARG_MIB((u32)0x15a8), 0xA); in ufs_hisi_pwr_change_pre_change()
328 ufshcd_dme_set(hba, UIC_ARG_MIB(0xD0A0), 0x10); in ufs_hisi_pwr_change_pre_change()
330 ufshcd_dme_set(hba, UIC_ARG_MIB(0x1556), 0x48); in ufs_hisi_pwr_change_pre_change()
334 ufshcd_dme_set(hba, UIC_ARG_MIB(0x15A8), 0x1); in ufs_hisi_pwr_change_pre_change()
336 ufshcd_dme_set(hba, UIC_ARG_MIB(0x155c), 0x0); in ufs_hisi_pwr_change_pre_change()
338 ufshcd_dme_set(hba, UIC_ARG_MIB(0x15b0), SZ_8K - 1); in ufs_hisi_pwr_change_pre_change()
[all …]
H A Dufs-exynos.c359 ufshcd_dme_set(hba, in exynos7_ufs_pre_link()
522 ufshcd_dme_set(hba, in exynos_ufs_set_pwm_clk_div()
667 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
670 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
673 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
676 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
679 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
682 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
689 ufshcd_dme_set(hba, in exynos_ufs_config_phy_cap_attr()
799 ufshcd_dme_set(hba, in exynos_ufs_config_sync_pattern_mask()
[all …]
H A Dufs-rockchip.c53 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(PA_LOCAL_TX_LCC_ENABLE, 0x0), 0x0); in ufs_rockchip_rk3576_phy_init()
55 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(MPHY_CFG, 0x0), MPHY_CFG_ENABLE); in ufs_rockchip_rk3576_phy_init()
58 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD, SEL_TX_LANE0 + i), 0x06); in ufs_rockchip_rk3576_phy_init()
67 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD, SEL_RX_LANE0 + i), 0x06); in ufs_rockchip_rk3576_phy_init()
77 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(MPHY_CFG, 0x0), MPHY_CFG_DISABLE); in ufs_rockchip_rk3576_phy_init()
118 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(MIB_T_DBG_CPORT_TX_ENDIAN, 0), 0x0); in ufs_rockchip_rk3576_phy_init()
119 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(MIB_T_DBG_CPORT_RX_ENDIAN, 0), 0x0); in ufs_rockchip_rk3576_phy_init()
120 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(N_DEVICEID, 0), 0x0); in ufs_rockchip_rk3576_phy_init()
121 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(N_DEVICEID_VALID, 0), 0x1); in ufs_rockchip_rk3576_phy_init()
122 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(T_PEERDEVICEID, 0), 0x1); in ufs_rockchip_rk3576_phy_init()
[all …]
H A Dcdns-pltfrm.c77 ufshcd_dme_set(hba, UIC_ARG_MIB(T_PEERDEVICEID), in cdns_ufs_set_l4_attr()
79 ufshcd_dme_set(hba, UIC_ARG_MIB(T_PEERCPORTID), in cdns_ufs_set_l4_attr()
81 ufshcd_dme_set(hba, UIC_ARG_MIB(T_TRAFFICCLASS), in cdns_ufs_set_l4_attr()
83 ufshcd_dme_set(hba, UIC_ARG_MIB(T_PROTOCOLID), in cdns_ufs_set_l4_attr()
85 ufshcd_dme_set(hba, UIC_ARG_MIB(T_CPORTFLAGS), in cdns_ufs_set_l4_attr()
87 ufshcd_dme_set(hba, UIC_ARG_MIB(T_TXTOKENVALUE), in cdns_ufs_set_l4_attr()
89 ufshcd_dme_set(hba, UIC_ARG_MIB(T_RXTOKENVALUE), in cdns_ufs_set_l4_attr()
93 ufshcd_dme_set(hba, UIC_ARG_MIB(T_PEERBUFFERSPACE), in cdns_ufs_set_l4_attr()
95 ufshcd_dme_set(hba, UIC_ARG_MIB(T_CREDITSTOSEND), in cdns_ufs_set_l4_attr()
97 ufshcd_dme_set(hba, UIC_ARG_MIB(T_CPORTMODE), in cdns_ufs_set_l4_attr()
[all …]
H A Dufs-sprd.c280 ufshcd_dme_set(hba, UIC_ARG_MIB(CBREFCLKCTRL2), 0x90); in ufs_sprd_n6_phy_init()
281 ufshcd_dme_set(hba, UIC_ARG_MIB(CBCRCTRL), 0x01); in ufs_sprd_n6_phy_init()
282 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RXSQCONTROL, in ufs_sprd_n6_phy_init()
284 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RXSQCONTROL, in ufs_sprd_n6_phy_init()
286 ufshcd_dme_set(hba, UIC_ARG_MIB(VS_MPHYCFGUPDT), 0x01); in ufs_sprd_n6_phy_init()
287 ufshcd_dme_set(hba, UIC_ARG_MIB(CBRATESEL), 0x01); in ufs_sprd_n6_phy_init()
295 ufshcd_dme_set(hba, UIC_ARG_MIB(CBCREGADDRLSB), 0x1c); in ufs_sprd_n6_phy_init()
297 ufshcd_dme_set(hba, UIC_ARG_MIB(CBCREGWRLSB), 0x04); in ufs_sprd_n6_phy_init()
298 ufshcd_dme_set(hba, UIC_ARG_MIB(CBCREGWRMSB), 0x00); in ufs_sprd_n6_phy_init()
315 ufshcd_dme_set(hba, UIC_ARG_MIB(VS_MPHYCFGUPDT), 0x01); in ufs_sprd_n6_phy_init()
[all …]
H A Dufs-exynos.h276 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OV_TM), true); in exynos_ufs_enable_ov_tm()
281 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OV_TM), false); in exynos_ufs_disable_ov_tm()
286 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_MODE), true); in exynos_ufs_enable_dbg_mode()
291 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_MODE), false); in exynos_ufs_disable_dbg_mode()
H A Dtc-dwc-g210.c267 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_MPHYCFGUPDT), 0x01); in tc_dwc_g210_config_40_bit()
272 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_DEBUGOMC), 0x01); in tc_dwc_g210_config_40_bit()
297 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_MPHYCFGUPDT), 0x01); in tc_dwc_g210_config_20_bit()
302 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_DEBUGOMC), 0x01); in tc_dwc_g210_config_20_bit()
H A Dufs-mediatek.c155 ufshcd_dme_set(hba, in ufs_mtk_cfg_unipro_cg()
161 ufshcd_dme_set(hba, in ufs_mtk_cfg_unipro_cg()
169 ufshcd_dme_set(hba, in ufs_mtk_cfg_unipro_cg()
175 ufshcd_dme_set(hba, in ufs_mtk_cfg_unipro_cg()
1108 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES), in ufs_mtk_pre_pwr_change()
1112 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES), in ufs_mtk_pre_pwr_change()
1115 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXHSADAPTTYPE), in ufs_mtk_pre_pwr_change()
1163 ret = ufshcd_dme_set(hba, in ufs_mtk_unipro_set_lpm()
1510 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 6); in ufs_mtk_apply_dev_quirks()
1511 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME), 10); in ufs_mtk_apply_dev_quirks()
[all …]
H A Dufs-qcom.c811 ret = ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_HS_EQUALIZER, i), in ufs_qcom_set_tx_hs_equalizer()
918 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CONFIG_REG1), in ufs_qcom_quirk_host_pa_saveconfigtime()
1360 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES), reg); in ufs_qcom_set_clk_40ns_cycles()
1408 err = ufshcd_dme_set(hba, in ufs_qcom_set_core_clk_ctrl()
1449 err = ufshcd_dme_set(hba, in ufs_qcom_clk_scale_down_pre_change()
/linux-6.15/drivers/ufs/core/
H A Dufshcd.c4051 ret = ufshcd_dme_set(hba, in ufshcd_dme_configure_adapt()
4387 ret = ufshcd_dme_set(hba, in ufshcd_uic_change_pwr_mode()
4632 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES), in ufshcd_change_power_mode()
4641 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES), in ufshcd_change_power_mode()
4653 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES), in ufshcd_change_power_mode()
4657 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), in ufshcd_change_power_mode()
4659 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), in ufshcd_change_power_mode()
4661 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), in ufshcd_change_power_mode()
4663 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA3), in ufshcd_change_power_mode()
4940 err = ufshcd_dme_set(hba, in ufshcd_disable_tx_lcc()
[all …]
/linux-6.15/include/ufs/
H A Dufshcd.h1403 static inline int ufshcd_dme_set(struct ufs_hba *hba, u32 attr_sel, in ufshcd_dme_set() function
1453 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0); in ufshcd_disable_host_tx_lcc()