Home
last modified time | relevance | path

Searched refs:transfers (Results 1 – 25 of 259) sorted by relevance

1234567891011

/linux-6.15/drivers/media/platform/amphion/
H A Dvpu_color.c79 u32 vpu_color_cvrt_transfers_v2i(u32 transfers) in vpu_color_cvrt_transfers_v2i() argument
84 u32 vpu_color_cvrt_transfers_i2v(u32 transfers) in vpu_color_cvrt_transfers_i2v() argument
86 return transfers < ARRAY_SIZE(colortransfers) ? colortransfers[transfers] : 0; in vpu_color_cvrt_transfers_i2v()
117 int vpu_color_check_transfers(u32 transfers) in vpu_color_check_transfers() argument
145 u32 transfers; in vpu_color_get_default() local
151 transfers = V4L2_XFER_FUNC_709; in vpu_color_get_default()
157 transfers = V4L2_XFER_FUNC_709; in vpu_color_get_default()
161 transfers = V4L2_XFER_FUNC_SMPTE240M; in vpu_color_get_default()
165 transfers = V4L2_XFER_FUNC_709; in vpu_color_get_default()
169 transfers = V4L2_XFER_FUNC_DEFAULT; in vpu_color_get_default()
[all …]
H A Dvpu_helpers.h58 int vpu_color_check_transfers(u32 transfers);
63 u32 vpu_color_cvrt_transfers_v2i(u32 transfers);
64 u32 vpu_color_cvrt_transfers_i2v(u32 transfers);
/linux-6.15/drivers/spi/
H A Dspi-loopback-test.c94 .transfers = {
108 .transfers = {
121 .transfers = {
133 .transfers = {
146 .transfers = {
163 .transfers = {
180 .transfers = {
197 .transfers = {
213 .transfers = {
230 .transfers = {
[all …]
H A Dspi-axi-spi-engine.c269 list_for_each_entry(xfer, &msg->transfers, transfer_list) { in spi_engine_precompile_message()
303 xfer = list_first_entry(&msg->transfers, struct spi_transfer, transfer_list); in spi_engine_compile_message()
306 list_for_each_entry(xfer, &msg->transfers, transfer_list) { in spi_engine_compile_message()
328 if (list_is_last(&xfer->transfer_list, &msg->transfers)) { in spi_engine_compile_message()
341 } else if (!list_is_last(&xfer->transfer_list, &msg->transfers) && in spi_engine_compile_message()
365 xfer = list_first_entry(&msg->transfers, in spi_engine_xfer_next()
367 } else if (list_is_last(&xfer->transfer_list, &msg->transfers)) { in spi_engine_xfer_next()
589 list_for_each_entry(xfer, &msg->transfers, transfer_list) { in spi_engine_offload_prepare()
623 list_for_each_entry(xfer, &msg->transfers, transfer_list) { in spi_engine_offload_prepare()
787 list_for_each_entry(xfer, &msg->transfers, transfer_list) in spi_engine_transfer_one_message()
[all …]
H A Dspi-fsl-espi.c160 first = list_first_entry(&m->transfers, struct spi_transfer, in fsl_espi_check_message()
163 list_for_each_entry(t, &m->transfers, transfer_list) { in fsl_espi_check_message()
198 list_for_each_entry(t, &m->transfers, transfer_list) { in fsl_espi_check_rxskip_mode()
406 espi->m_transfers = &m->transfers; in fsl_espi_trans()
407 espi->tx_t = list_first_entry(&m->transfers, struct spi_transfer, in fsl_espi_trans()
411 espi->rx_t = list_first_entry(&m->transfers, struct spi_transfer, in fsl_espi_trans()
446 list_for_each_entry(t, &m->transfers, transfer_list) { in fsl_espi_do_one_msg()
455 t = list_first_entry(&m->transfers, struct spi_transfer, in fsl_espi_do_one_msg()
H A Dspi-bcm63xx-hsspi.c283 list_for_each_entry(t, &msg->transfers, transfer_list) { in bcm63xx_prepare_prepend_transfer()
301 !list_is_last(&t->transfer_list, &msg->transfers)) { in bcm63xx_prepare_prepend_transfer()
312 if (!list_is_last(&t->transfer_list, &msg->transfers)) { in bcm63xx_prepare_prepend_transfer()
319 if (list_is_last(&t->transfer_list, &msg->transfers)) { in bcm63xx_prepare_prepend_transfer()
606 list_for_each_entry(t, &msg->transfers, transfer_list) { in bcm63xx_hsspi_do_dummy_cs_txrx()
632 if (list_is_last(&t->transfer_list, &msg->transfers)) { in bcm63xx_hsspi_do_dummy_cs_txrx()
643 } else if (!list_is_last(&t->transfer_list, &msg->transfers) && in bcm63xx_hsspi_do_dummy_cs_txrx()
H A Dspi-cavium.c135 list_for_each_entry(xfer, &msg->transfers, transfer_list) { in octeon_spi_transfer_one_message()
137 &msg->transfers); in octeon_spi_transfer_one_message()
/linux-6.15/Documentation/i2c/
H A Di2c-topology.rst25 I2C transfers, and all adapters with a parent are part of an "i2c-mux"
49 select and/or deselect operations must use I2C transfers to complete
74 4. M1 (presumably) does some I2C transfers as part of its select.
75 These transfers are normal I2C transfers that locks the parent
114 number (one, in most cases) of I2C transfers. Unrelated I2C transfers
130 has to ensure that any and all I2C transfers through that parent
155 its select, those transfers must be unlocked I2C transfers so
178 and the parent mux issues I2C transfers as part of its select).
184 pinctrl, regmap or iio, it is essential that any I2C transfers
263 as partial I2C transfers, i.e. garbage or worse. This might cause
[all …]
/linux-6.15/Documentation/usb/
H A Dohci.rst22 - interrupt transfers can be larger, and can be queued
29 transfers. Previously, using periods of one frame would risk data loss due
30 to overhead in IRQ processing. When interrupt transfers are queued, those
31 risks can be minimized by making sure the hardware always has transfers to
H A Dehci.rst59 and interrupt transfers, including requests to USB 1.1 devices through
67 transfers can't share much code with the code for high speed ISO transfers,
74 Transfers of all types can be queued. This means that control transfers
76 ones from another driver, and that interrupt transfers can use periods
88 transactions (interrupt and isochronous transfers). These place some
125 and bulk transfers. Shows each active qh and the qtds
130 and isochronous transfers. Doesn't show qtds.
140 can't, such as "high bandwidth" periodic (interrupt or ISO) transfers.
160 Bulk transfers are most often used where throughput is an issue. It's
165 So more than 50 MByte/sec is available for bulk transfers, when both
[all …]
/linux-6.15/Documentation/driver-api/dmaengine/
H A Dprovider.rst11 They have a given number of channels to use for the DMA transfers, and
44 transfer into smaller sub-transfers.
48 transfers we usually have are not, and want to copy data from
52 DMAEngine, at least for mem2dev transfers, require support for
91 Over time, the need for memory to device transfers arose, and
125 (i.e. excluding mem2mem transfers)
216 available for async transfers.
228 scatter-gather transfers.
240 - The device can handle cyclic transfers.
541 ignored in the slave transfers case.
[all …]
H A Dpxa_dma.rst19 b) All transfers having asked for confirmation should be signaled
115 This will speed up residue calculation, for large transfers such as video
129 - calling all the transfer callbacks of finished transfers, based on
138 transfers will be scanned for all of their descriptors against the
144 - there are not "acked" transfers (tx0)
/linux-6.15/Documentation/ABI/testing/
H A Dsysfs-bus-mdio10 What: /sys/bus/mdio_bus/devices/.../statistics/transfers
11 What: /sys/class/mdio_bus/.../transfers
16 Total number of transfers for this MDIO bus.
48 Total number of transfers for this MDIO bus address.
H A Dsysfs-bus-fsi-devices-sbefifo8 occurred and no transfers have completed since the timeout. A
10 has, more recent transfers have completed successfully.
/linux-6.15/Documentation/devicetree/bindings/dma/stm32/
H A Dst,stm32-dma.yaml20 0x0: no address increment between transfers
21 0x1: increment address between transfers
23 0x0: no address increment between transfers
24 0x1: increment address between transfers
49 managing transfers for STM32 USART/UART.
H A Dst,stm32-dma3.yaml66 -bit 4-7: The FIFO requirement for queuing source/destination transfers
102 -bit 17: Prevent additional transfers due to linked-list refactoring
103 0x0: don't prevent additional transfers for optimal performance
/linux-6.15/Documentation/core-api/
H A Ddma-isa-lpc.rst7 This document describes how to do DMA transfers using the old ISA DMA
22 The second contains the routines specific to ISA DMA transfers. Since
34 (You usually need a special buffer for DMA transfers instead of
69 8-bit transfers and the upper four are for 16-bit transfers.
80 The ability to use 16-bit or 8-bit transfers is _not_ up to you as a
105 be 16-bit aligned for 16-bit transfers) and how many bytes to
/linux-6.15/Documentation/devicetree/bindings/dma/
H A Datmel,at91sam9g45-dma.yaml13 The Atmel Direct Memory Access Controller (DMAC) transfers data from a source
17 the data from a source and writes it to a destination. Two AMBA transfers are
38 2. The second cell is 0 for RX and 1 for TX transfers.
H A Dst_fdma.txt59 0x0: no address increment between transfers
60 0x1: increment address between transfers
64 4. transfers type
/linux-6.15/drivers/usb/gadget/udc/
H A DKconfig142 zero (for control transfers).
163 supports both full and high speed USB 2.0 data transfers.
225 control transfers).
284 supports both full and high speed USB 2.0 data transfers.
334 both full and high speed USB 2.0 data transfers.
357 supports both full and high speed USB 2.0 data transfers.
360 (for control transfers) and several endpoints with dedicated
367 data transfers.
385 endpoints, plus endpoint zero (for control transfers).
402 supports both full and high speed USB 2.0 data transfers.
[all …]
/linux-6.15/Documentation/driver-api/soundwire/
H A Dbra.rst15 command/control transfers by reclaiming parts of the audio
32 efficiency of the protocol by requiring multiple BRA transfers
41 bandwidth. If there are no on-going audio transfers, the entire
53 BRA transfers. This is convenient to e.g. deal with alerts, jack
60 bus behind the SoundWire IP. In this case, the transfers may
181 with two FIFOs consuming/generating data transfers in parallel
226 However BRA transfers could be quite long, and the use of a single
228 operation of the control/command and BRA transfers is a fundamental
242 to wait for the BRA transfers to complete. This would allow for a
284 For regular audio transfers, the machine driver exposes a dailink
[all …]
/linux-6.15/Documentation/driver-api/usb/
H A DURB.rst67 // (IN) buffer used for data transfers
78 // Only for PERIODIC transfers (ISO, INTERRUPT)
150 - Too many queued ISO transfers (``-EAGAIN``)
224 transferred. That's because USB transfers are packetized; it might take
239 How to do isochronous (ISO) transfers?
243 have to set ``urb->interval`` to say how often to make transfers; it's
249 For ISO transfers you also have to fill a :c:type:`usb_iso_packet_descriptor`
275 How to start interrupt (INT) transfers?
278 Interrupt transfers, like isochronous transfers, are periodic, and happen
/linux-6.15/drivers/rapidio/
H A DKconfig35 than Maintenance transfers.
44 transfers to/from target RIO devices. RapidIO uses NREAD and
47 capable to perform data transfers to/from RapidIO.
/linux-6.15/Documentation/driver-api/rapidio/
H A Dmport_cdev.rst49 - Allocate/Free contiguous DMA coherent memory buffer for DMA data transfers
51 - Initiate DMA data transfers to/from remote RapidIO devices (RIO_TRANSFER).
75 specific DMA engine support and therefore DMA data transfers mport_cdev driver
109 - Add memory mapped DMA data transfers as an option when RapidIO-specific DMA
/linux-6.15/Documentation/devicetree/bindings/dma/xilinx/
H A Dxlnx,zynqmp-dma-1.0.yaml10 The Xilinx ZynqMP DMA engine supports memory to memory transfers,
11 memory to device and device to memory transfers. It also has flow

1234567891011