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Searched refs:train_set (Results 1 – 12 of 12) sorted by relevance

/linux-6.15/drivers/gpu/drm/hisilicon/hibmc/dp/
H A Ddp_link.c98 u8 *train_set = dp->link.train_set; in hibmc_dp_link_training_cr_pre() local
111 train_set[i] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2; in hibmc_dp_link_training_cr_pre()
113 ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, train_set, dp->link.cap.lanes); in hibmc_dp_link_training_cr_pre()
125 u8 train_set[HIBMC_DP_LANE_NUM_MAX] = {0}; in hibmc_dp_link_get_adjust_train() local
129 train_set[lane] = drm_dp_get_adjust_request_voltage(lane_status, lane) | in hibmc_dp_link_get_adjust_train()
132 if (memcmp(dp->link.train_set, train_set, HIBMC_DP_LANE_NUM_MAX)) { in hibmc_dp_link_get_adjust_train()
133 memcpy(dp->link.train_set, train_set, HIBMC_DP_LANE_NUM_MAX); in hibmc_dp_link_get_adjust_train()
209 ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, dp->link.train_set, in hibmc_dp_link_training_cr()
259 dp->link.train_set, dp->link.cap.lanes); in hibmc_dp_link_training_channel_eq()
H A Ddp_comm.h30 u8 train_set[HIBMC_DP_LANE_NUM_MAX]; member
/linux-6.15/drivers/gpu/drm/i915/display/
H A Dg4x_dp.c826 u8 train_set = intel_dp->train_set[0]; in vlv_set_signal_levels() local
828 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { in vlv_set_signal_levels()
912 u8 train_set = intel_dp->train_set[0]; in chv_set_signal_levels() local
914 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { in chv_set_signal_levels()
989 static u32 g4x_signal_levels(u8 train_set) in g4x_signal_levels() argument
1008 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { in g4x_signal_levels()
1032 u8 train_set = intel_dp->train_set[0]; in g4x_set_signal_levels() local
1035 signal_levels = g4x_signal_levels(train_set); in g4x_set_signal_levels()
1048 static u32 snb_cpu_edp_signal_levels(u8 train_set) in snb_cpu_edp_signal_levels() argument
1080 u8 train_set = intel_dp->train_set[0]; in snb_cpu_edp_set_signal_levels() local
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H A Dintel_dp_link_training.c504 intel_dp->train_set[lane] = in intel_dp_get_adjust_train()
524 u8 buf[sizeof(intel_dp->train_set) + 1]; in intel_dp_set_link_train()
572 #define TRAIN_SET_VSWING_ARGS(train_set) \ argument
573 _TRAIN_SET_VSWING_ARGS((train_set)[0]), \
574 _TRAIN_SET_VSWING_ARGS((train_set)[1]), \
575 _TRAIN_SET_VSWING_ARGS((train_set)[2]), \
576 _TRAIN_SET_VSWING_ARGS((train_set)[3])
584 _TRAIN_SET_PREEMPH_ARGS((train_set)[3])
587 #define TRAIN_SET_TX_FFE_ARGS(train_set) \ argument
591 _TRAIN_SET_TX_FFE_ARGS((train_set)[3])
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H A Dintel_dp_test.c330 intel_dp->train_set, crtc_state->lane_count); in intel_dp_process_phy_request()
701 intel_dp->train_set[0]); in i915_displayport_test_data_show()
H A Dintel_ddi.c1477 u8 train_set = intel_dp->train_set[lane]; in intel_ddi_dp_level() local
1480 return train_set & DP_TX_FFE_PRESET_VALUE_MASK; in intel_ddi_dp_level()
1482 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | in intel_ddi_dp_level()
H A Dintel_display_types.h1725 u8 train_set[4]; member
H A Dintel_dp.c3225 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); in intel_dp_set_link_params()
/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Datombios_dp.c205 u8 train_set[4]) in amdgpu_atombios_dp_get_adjust_train()
237 train_set[lane] = v | p; in amdgpu_atombios_dp_get_adjust_train()
496 u8 train_set[4]; member
512 dp_info->train_set, dp_info->dp_lane_count); in amdgpu_atombios_dp_update_vs_emph()
606 memset(dp_info->train_set, 0, 4); in amdgpu_atombios_dp_link_train_cr()
651 dp_info->train_set); in amdgpu_atombios_dp_link_train_cr()
660 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, in amdgpu_atombios_dp_link_train_cr()
661 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> in amdgpu_atombios_dp_link_train_cr()
702 dp_info->train_set); in amdgpu_atombios_dp_link_train_ce()
713 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, in amdgpu_atombios_dp_link_train_ce()
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/linux-6.15/drivers/gpu/drm/radeon/
H A Datombios_dp.c254 u8 train_set[4]) in dp_get_adjust_train()
286 train_set[lane] = v | p; in dp_get_adjust_train()
541 u8 train_set[4]; member
557 dp_info->train_set, dp_info->dp_lane_count); in radeon_dp_update_vs_emph()
668 memset(dp_info->train_set, 0, 4); in radeon_dp_link_train_cr()
692 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) in radeon_dp_link_train_cr()
709 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in radeon_dp_link_train_cr()
721 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, in radeon_dp_link_train_cr()
722 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> in radeon_dp_link_train_cr()
772 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, in radeon_dp_link_train_ce()
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/linux-6.15/drivers/gpu/drm/xlnx/
H A Dzynqmp_dp.c332 u8 train_set[ZYNQMP_DP_MAX_LANES]; member
407 u8 train_set[ZYNQMP_DP_MAX_LANES]; member
697 u8 *train_set = dp->train_set; in zynqmp_dp_adjust_train() local
711 train_set[i] = voltage | preemphasis; in zynqmp_dp_adjust_train()
739 u8 train = train_set[i]; in zynqmp_dp_update_vs_emph()
957 memset(dp->train_set, 0, sizeof(dp->train_set)); in zynqmp_dp_train()
2095 u8 *train_set = &dp->test.train_set[priv->lane]; in zynqmp_dp_swing_set() local
2103 *train_set |= val; in zynqmp_dp_swing_set()
2123 dp->test.train_set[priv->lane]); in zynqmp_dp_preemphasis_get()
2131 u8 *train_set = &dp->test.train_set[priv->lane]; in zynqmp_dp_preemphasis_set() local
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/linux-6.15/drivers/gpu/drm/gma500/
H A Dcdv_intel_dp.c267 uint8_t train_set[4]; member
1296 intel_dp->train_set[lane] = v | p; in cdv_intel_get_adjust_train()
1385 intel_dp->train_set, in cdv_intel_dplink_set_level()
1390 intel_dp->train_set[0], intel_dp->lane_count); in cdv_intel_dplink_set_level()
1490 memset(intel_dp->train_set, 0, 4); in cdv_intel_dp_start_link_train()
1501 intel_dp->train_set[0], in cdv_intel_dp_start_link_train()
1508 cdv_intel_dp_set_vswing_premph(encoder, intel_dp->train_set[0]); in cdv_intel_dp_start_link_train()
1529 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) in cdv_intel_dp_start_link_train()
1541 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in cdv_intel_dp_start_link_train()
1574 intel_dp->train_set[0], in cdv_intel_dp_complete_link_train()
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