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Searched refs:tmds_div (Results 1 – 4 of 4) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/display/dc/dccg/dcn401/
H A Ddcn401_dccg.c122 uint32_t *tmds_div, in dccg401_get_pixel_rate_div() argument
154 *tmds_div = val_tmds_div == 0 ? PIXEL_RATE_DIV_BY_2 : PIXEL_RATE_DIV_BY_4; in dccg401_get_pixel_rate_div()
160 enum pixel_rate_div tmds_div, in dccg401_set_pixel_rate_div() argument
169 if (tmds_div != PIXEL_RATE_DIV_BY_2 && tmds_div != PIXEL_RATE_DIV_BY_4) { in dccg401_set_pixel_rate_div()
174 if (tmds_div == cur_tmds_div) in dccg401_set_pixel_rate_div()
178 reg_val = tmds_div == PIXEL_RATE_DIV_BY_4 ? 1 : 0; in dccg401_set_pixel_rate_div()
H A Ddcn401_dccg.h221 enum pixel_rate_div tmds_div,
226 uint32_t *tmds_div,
/linux-6.15/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_hwseq.c670 unsigned int *tmds_div) in dcn401_calculate_dccg_tmds_div_value() argument
676 *tmds_div = PIXEL_RATE_DIV_BY_2; in dcn401_calculate_dccg_tmds_div_value()
678 *tmds_div = PIXEL_RATE_DIV_BY_4; in dcn401_calculate_dccg_tmds_div_value()
680 *tmds_div = PIXEL_RATE_DIV_BY_1; in dcn401_calculate_dccg_tmds_div_value()
683 if (*tmds_div == PIXEL_RATE_DIV_NA) in dcn401_calculate_dccg_tmds_div_value()
692 unsigned int *tmds_div, in enable_stream_timing_calc() argument
757 tmds_div, unused_div); in dcn401_enable_stream_timing()
881 unsigned int *tmds_div, in dcn401_enable_stream_calc() argument
899 *tmds_div = PIXEL_RATE_DIV_BY_1; in dcn401_enable_stream_calc()
934 &tmds_div, &early_control); in dcn401_enable_stream()
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H A Ddcn401_hwseq.h46 unsigned int *tmds_div);