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Searched refs:tf_mask (Results 1 – 25 of 38) sorted by relevance

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/linux-6.15/drivers/gpu/drm/amd/display/dc/dpp/dcn10/
H A Ddcn10_dpp_cm.c50 dpp->tf_shift->field_name, dpp->tf_mask->field_name
119 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; in program_gamut_remap()
121 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12; in program_gamut_remap()
197 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; in read_gamut_remap()
199 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12; in read_gamut_remap()
282 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_OCSC_C11; in dpp1_cm_program_color_matrix()
284 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_OCSC_C12; in dpp1_cm_program_color_matrix()
338 reg->masks.field_region_end = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_B; in dpp1_cm_get_reg_field()
539 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_ICSC_C11; in dpp1_program_input_csc()
541 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_ICSC_C12; in dpp1_program_input_csc()
[all …]
H A Ddcn10_dpp.c49 dpp->tf_shift->field_name, dpp->tf_mask->field_name
513 if (dpp->tf_mask->DPPCLK_RATE_CONTROL) in dpp1_dppclk_control()
569 const struct dcn_dpp_mask *tf_mask) in dpp1_construct() argument
579 dpp->tf_mask = tf_mask; in dpp1_construct()
H A Ddcn10_dpp_dscl.c51 dpp->tf_shift->field_name, dpp->tf_mask->field_name
364 scl_mode, dpp->tf_mask->SCL_COEF_RAM_SELECT_CURRENT, in dpp1_dscl_set_scl_filter()
/linux-6.15/drivers/gpu/drm/amd/display/dc/dpp/dcn30/
H A Ddcn30_dpp_cm.c41 dpp->tf_shift->field_name, dpp->tf_mask->field_name
176 reg->masks.field_offset = dpp->tf_mask->CM_GAMCOR_RAMA_OFFSET_B; in dpp3_gamcor_reg_field()
179 reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET; in dpp3_gamcor_reg_field()
183 reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET; in dpp3_gamcor_reg_field()
188 reg->masks.field_region_end = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_END_B; in dpp3_gamcor_reg_field()
192 reg->masks.field_region_end_base = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B; in dpp3_gamcor_reg_field()
196 reg->masks.exp_region_start = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_START_B; in dpp3_gamcor_reg_field()
342 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; in program_gamut_remap()
344 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12; in program_gamut_remap()
422 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; in read_gamut_remap()
[all …]
H A Ddcn30_dpp.c41 dpp->tf_shift->field_name, dpp->tf_mask->field_name
135 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_POST_CSC_C11; in dpp3_program_post_csc()
137 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_POST_CSC_C12; in dpp3_program_post_csc()
675 reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dcn3_dpp_cm_get_reg_field()
679 reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET; in dcn3_dpp_cm_get_reg_field()
684 reg->masks.field_region_end = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_B; in dcn3_dpp_cm_get_reg_field()
686 reg->masks.field_region_end_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B; in dcn3_dpp_cm_get_reg_field()
688 reg->masks.field_region_end_base = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B; in dcn3_dpp_cm_get_reg_field()
692 reg->masks.exp_region_start = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_B; in dcn3_dpp_cm_get_reg_field()
1514 const struct dcn3_dpp_mask *tf_mask) in dpp3_construct() argument
[all …]
H A Ddcn30_dpp.h565 const struct dcn3_dpp_mask *tf_mask; member
585 const struct dcn3_dpp_mask *tf_mask);
/linux-6.15/drivers/gpu/drm/amd/display/dc/dpp/dcn35/
H A Ddcn35_dpp.c38 ((const struct dcn35_dpp_mask *)(dpp->tf_mask))->field_name
48 if (dpp->tf_mask->DPPCLK_RATE_CONTROL) in dpp35_dppclk_control()
132 const struct dcn35_dpp_mask *tf_mask) in dpp35_construct() argument
136 (const struct dcn3_dpp_mask *)(tf_mask)); in dpp35_construct()
H A Ddcn35_dpp.h60 const struct dcn35_dpp_mask *tf_mask);
/linux-6.15/drivers/gpu/drm/amd/display/dc/dpp/dcn401/
H A Ddcn401_dpp_cm.c50 dpp->tf_shift->field_name, dpp->tf_mask->field_name
106 if (dpp->tf_mask->CM_BYPASS_EN) in dpp401_full_bypass()
224 cur_matrix_regs.masks.csc_c11 = dpp->tf_mask->CUR0_MATRIX_C11_A; in dpp401_program_cursor_csc()
226 cur_matrix_regs.masks.csc_c12 = dpp->tf_mask->CUR0_MATRIX_C12_A; in dpp401_program_cursor_csc()
H A Ddcn401_dpp.c43 dpp->tf_shift->field_name, dpp->tf_mask->field_name
267 const struct dcn401_dpp_mask *tf_mask) in dpp401_construct() argument
277 dpp->tf_mask = tf_mask; in dpp401_construct()
H A Ddcn401_dpp.h661 const struct dcn401_dpp_mask *tf_mask; member
680 const struct dcn401_dpp_mask *tf_mask);
H A Ddcn401_dpp_dscl.c51 dpp->tf_shift->field_name, dpp->tf_mask->field_name
378 scl_mode, dpp->tf_mask->SCL_COEF_RAM_SELECT_CURRENT, in dpp401_dscl_set_scl_filter()
/linux-6.15/drivers/gpu/drm/amd/display/dc/dpp/dcn20/
H A Ddcn20_dpp_cm.c47 dpp->tf_shift->field_name, dpp->tf_mask->field_name
190 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; in program_gamut_remap()
192 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12; in program_gamut_remap()
251 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; in read_gamut_remap()
253 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12; in read_gamut_remap()
340 icsc_regs.masks.csc_c11 = dpp->tf_mask->CM_ICSC_C11; in dpp2_program_input_csc()
342 icsc_regs.masks.csc_c12 = dpp->tf_mask->CM_ICSC_C12; in dpp2_program_input_csc()
418 reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dcn20_dpp_cm_get_reg_field()
427 reg->masks.field_region_end = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_B; in dcn20_dpp_cm_get_reg_field()
431 reg->masks.field_region_end_base = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B; in dcn20_dpp_cm_get_reg_field()
[all …]
H A Ddcn20_dpp.c49 dpp->tf_shift->field_name, dpp->tf_mask->field_name
412 const struct dcn2_dpp_mask *tf_mask) in dpp2_construct() argument
422 dpp->tf_mask = tf_mask; in dpp2_construct()
H A Ddcn20_dpp.h682 const struct dcn2_dpp_mask *tf_mask; member
780 const struct dcn2_dpp_mask *tf_mask);
/linux-6.15/drivers/gpu/drm/amd/display/dc/dpp/dcn201/
H A Ddcn201_dpp.h62 const struct dcn201_dpp_mask *tf_mask; member
81 const struct dcn201_dpp_mask *tf_mask);
H A Ddcn201_dpp.c42 dpp->tf_shift->field_name, dpp->tf_mask->field_name
303 const struct dcn201_dpp_mask *tf_mask) in dpp201_construct() argument
313 dpp->tf_mask = tf_mask; in dpp201_construct()
/linux-6.15/drivers/gpu/drm/amd/display/dc/dpp/dcn32/
H A Ddcn32_dpp.c152 const struct dcn3_dpp_mask *tf_mask) in dpp32_construct() argument
162 dpp->tf_mask = tf_mask; in dpp32_construct()
H A Ddcn32_dpp.h36 const struct dcn3_dpp_mask *tf_mask);
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn201/
H A Ddcn201_resource.c479 static const struct dcn201_dpp_mask tf_mask = { variable
638 &tf_regs[inst], &tf_shift, &tf_mask)) in dcn201_dpp_create()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn303/
H A Ddcn303_resource.c512 static const struct dcn3_dpp_mask tf_mask = { variable
523 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn303_dpp_create()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn302/
H A Ddcn302_resource.c533 static const struct dcn3_dpp_mask tf_mask = { variable
544 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn302_dpp_create()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn10/
H A Ddcn10_resource.c365 static const struct dcn_dpp_mask tf_mask = { variable
579 &tf_regs[inst], &tf_shift, &tf_mask); in dcn10_dpp_create()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn301/
H A Ddcn301_resource.c419 static const struct dcn3_dpp_mask tf_mask = { variable
723 &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn301_dpp_create()
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn21/
H A Ddcn21_resource.c447 static const struct dcn2_dpp_mask tf_mask = { variable
510 &tf_regs[inst], &tf_shift, &tf_mask)) in dcn21_dpp_create()

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