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Searched refs:tc_port (Results 1 – 12 of 12) sorted by relevance

/linux-6.15/drivers/gpu/drm/i915/display/
H A Dintel_dkl_phy_regs.h29 #define _DKL_REG_PHY_BASE(tc_port) _PORT(tc_port, \ argument
51 #define DKL_PCS_DW5(tc_port, ln) _DKL_REG_LN(tc_port, ln, \ argument
57 #define DKL_PLL_DIV0(tc_port) _DKL_REG(tc_port, \ argument
76 #define DKL_PLL_DIV1(tc_port) _DKL_REG(tc_port, \ argument
84 #define DKL_PLL_SSC(tc_port) _DKL_REG(tc_port, \ argument
95 #define DKL_PLL_BIAS(tc_port) _DKL_REG(tc_port, \ argument
103 #define DKL_PLL_TDC_COLDST_BIAS(tc_port) _DKL_REG(tc_port, \ argument
111 #define DKL_REFCLKIN_CTL(tc_port) _DKL_REG(tc_port, \ argument
121 #define DKL_CLKTOP2_CORECLKCTL1(tc_port) _DKL_REG(tc_port, \ argument
187 #define DKL_CMN_UC_DW_27(tc_port) _DKL_REG(tc_port, \ argument
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H A Dintel_mg_phy_regs.h105 #define MG_CLKHUB(ln, tc_port) \ argument
163 #define MG_REFCLKIN_CTL(tc_port) _MMIO_PORT((tc_port), \ argument
173 #define MG_CLKTOP2_CORECLKCTL1(tc_port) _MMIO_PORT((tc_port), \ argument
191 #define MG_CLKTOP2_HSCLKCTL(tc_port) _MMIO_PORT((tc_port), \ argument
203 #define MG_PLL_DIV0(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV0_PORT1, \ argument
216 #define MG_PLL_DIV1(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV1_PORT1, \ argument
227 #define MG_PLL_LF(tc_port) _MMIO_PORT((tc_port), _MG_PLL_LF_PORT1, \ argument
238 #define MG_PLL_FRAC_LOCK(tc_port) _MMIO_PORT((tc_port), \ argument
250 #define MG_PLL_SSC(tc_port) _MMIO_PORT((tc_port), _MG_PLL_SSC_PORT1, \ argument
268 #define MG_PLL_BIAS(tc_port) _MMIO_PORT((tc_port), _MG_PLL_BIAS_PORT1, \ argument
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H A Dintel_dkl_phy.c25 enum tc_port tc_port = DKL_REG_TC_PORT(reg); in dkl_phy_set_hip_idx() local
27 drm_WARN_ON(display->drm, tc_port < TC_PORT_1 || tc_port >= I915_MAX_TC_PORTS); in dkl_phy_set_hip_idx()
30 HIP_INDEX_REG(tc_port), in dkl_phy_set_hip_idx()
31 HIP_INDEX_VAL(tc_port, reg.bank_idx)); in dkl_phy_set_hip_idx()
H A Dintel_dpll_mgr.c198 enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port) in icl_tc_port_to_pll_id() argument
221 enum tc_port tc_port = icl_pll_id_to_tc_port(id); in intel_tc_pll_enable_reg() local
224 return ADLP_PORTTC_PLL_ENABLE(tc_port); in intel_tc_pll_enable_reg()
226 return MG_PLL_ENABLE(tc_port); in intel_tc_pll_enable_reg()
3549 enum tc_port tc_port = icl_pll_id_to_tc_port(id); in mg_pll_get_hw_state() local
3566 MG_REFCLKIN_CTL(tc_port)); in mg_pll_get_hw_state()
3586 MG_PLL_FRAC_LOCK(tc_port)); in mg_pll_get_hw_state()
3616 enum tc_port tc_port = icl_pll_id_to_tc_port(id); in dkl_pll_get_hw_state() local
3635 DKL_REFCLKIN_CTL(tc_port)); in dkl_pll_get_hw_state()
3805 enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id); in icl_mg_pll_write() local
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H A Dintel_ddi.c1291 enum tc_port tc_port = intel_encoder_to_tc(encoder); in icl_mg_phy_set_signal_levels() local
1392 enum tc_port tc_port = intel_encoder_to_tc(encoder); in tgl_dkl_phy_set_signal_levels() local
1831 enum tc_port tc_port = intel_encoder_to_tc(encoder); in icl_ddi_tc_enable_clock() local
1851 enum tc_port tc_port = intel_encoder_to_tc(encoder); in icl_ddi_tc_disable_clock() local
1867 enum tc_port tc_port = intel_encoder_to_tc(encoder); in icl_ddi_tc_is_clock_enabled() local
1884 enum tc_port tc_port = intel_encoder_to_tc(encoder); in icl_ddi_tc_get_pll() local
2147 enum tc_port tc_port, u32 ln0, u32 ln1) in tgl_dkl_phy_check_and_rewrite() argument
3708 enum tc_port tc_port = intel_encoder_to_tc(encoder); in adlp_tbt_to_dp_alt_switch_wa() local
5016 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1') argument
5165 enum tc_port tc_port = intel_port_to_tc(display, port); in intel_ddi_init() local
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H A Dintel_tc.c253 enum tc_port tc_port = intel_encoder_to_tc(&tc->dig_port->base); in tc_port_power_domain() local
301 enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base); in lnl_tc_port_get_max_lane_count() local
306 val = intel_de_read(i915, TCSS_DDI_STATUS(tc_port)); in lnl_tc_port_get_max_lane_count()
459 enum tc_port tc_port = intel_encoder_to_tc(&tc->dig_port->base); in tc_phy_load_fia_params() local
466 tc->phy_fia = tc_port / 2; in tc_phy_load_fia_params()
467 tc->phy_fia_idx = tc_port % 2; in tc_phy_load_fia_params()
470 tc->phy_fia_idx = tc_port; in tc_phy_load_fia_params()
814 enum tc_port tc_port = intel_encoder_to_tc(&tc->dig_port->base); in adlp_tc_phy_is_ready() local
819 val = intel_de_read(i915, TCSS_DDI_STATUS(tc_port)); in adlp_tc_phy_is_ready()
1891 enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base); in intel_tc_port_init() local
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H A Dintel_dpll_mgr.h37 enum tc_port;
435 enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port);
H A Dintel_display.h141 enum tc_port { enum
469 enum tc_port intel_port_to_tc(struct intel_display *display, enum port port);
475 enum tc_port intel_encoder_to_tc(struct intel_encoder *encoder);
H A Dintel_display_power_well.c537 enum tc_port tc_port; in icl_tc_phy_aux_power_well_enable() local
539 tc_port = TGL_AUX_PW_TO_TC_PORT(i915_power_well_instance(power_well)->hsw.idx); in icl_tc_phy_aux_power_well_enable()
541 if (wait_for(intel_dkl_phy_read(display, DKL_CMN_UC_DW_27(tc_port)) & in icl_tc_phy_aux_power_well_enable()
H A Dintel_display.c1886 enum tc_port intel_port_to_tc(struct intel_display *display, enum port port) in intel_port_to_tc()
1925 enum tc_port intel_encoder_to_tc(struct intel_encoder *encoder) in intel_encoder_to_tc()
/linux-6.15/drivers/gpu/drm/i915/
H A Di915_reg.h3899 #define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < TC_PORT_4 ? \ argument
3900 (tc_port) + 12 : \
3901 (tc_port) - TC_PORT_4 + 21))
3976 #define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \ argument
3987 #define ADLP_PORTTC_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), \ argument
/linux-6.15/drivers/platform/chrome/
H A Dcros_ec_typec.c45 static int cros_typec_enter_usb_mode(struct typec_port *tc_port, enum usb_mode mode) in cros_typec_enter_usb_mode() argument
47 struct cros_typec_port *port = typec_get_drvdata(tc_port); in cros_typec_enter_usb_mode()