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Searched refs:sseu (Results 1 – 25 of 25) sorted by relevance

/linux-6.15/drivers/gpu/drm/i915/gt/
H A Dintel_sseu.c164 sseu->eu_total = compute_eu_total(sseu); in gen11_compute_sseu_info()
184 sseu->eu_total = compute_eu_total(sseu); in xehp_compute_sseu_info()
210 struct sseu_dev_info *sseu = &gt->info.sseu; in xehp_sseu_info_init() local
254 struct sseu_dev_info *sseu = &gt->info.sseu; in gen12_sseu_info_init() local
295 struct sseu_dev_info *sseu = &gt->info.sseu; in gen11_sseu_info_init() local
329 struct sseu_dev_info *sseu = &gt->info.sseu; in cherryview_sseu_info_init() local
355 sseu->eu_total = compute_eu_total(sseu); in cherryview_sseu_info_init()
378 struct sseu_dev_info *sseu = &gt->info.sseu; in gen9_sseu_info_init() local
435 sseu->eu_total = compute_eu_total(sseu); in gen9_sseu_info_init()
544 sseu->eu_total = compute_eu_total(sseu); in bdw_sseu_info_init()
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H A Dintel_sseu_debugfs.c88 sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s]; in gen11_sseu_device_status()
143 sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s]; in gen9_sseu_device_status()
178 sseu->eu_per_subslice = info->sseu.eu_per_subslice; in bdw_sseu_device_status()
180 sseu->subslice_mask.hsw[s] = info->sseu.subslice_mask.hsw[s]; in bdw_sseu_device_status()
181 sseu->eu_total = sseu->eu_per_subslice * in bdw_sseu_device_status()
201 sseu->slice_mask); in i915_print_sseu_info()
208 sseu->eu_total); in i915_print_sseu_info()
246 sseu = kzalloc(sizeof(*sseu), GFP_KERNEL); in intel_sseu_status()
247 if (!sseu) in intel_sseu_status()
250 intel_sseu_set_info(sseu, info->sseu.max_slices, in intel_sseu_status()
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H A Dintel_sseu.h112 .slice_mask = sseu->slice_mask, in intel_sseu_from_device_info()
113 .subslice_mask = sseu->subslice_mask.hsw[0], in intel_sseu_from_device_info()
125 if (slice >= sseu->max_slices || in intel_sseu_has_subslice()
126 subslice >= sseu->max_subslices) in intel_sseu_has_subslice()
129 if (sseu->has_xehp_dss) in intel_sseu_has_subslice()
144 return find_next_bit(sseu->subslice_mask.xehp, in intel_sseu_find_first_xehp_dss()
145 XEHP_BITMAP_BITS(sseu->subslice_mask), in intel_sseu_find_first_xehp_dss()
168 const struct sseu_dev_info *sseu,
174 const struct sseu_dev_info *sseu);
176 const struct sseu_dev_info *sseu);
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H A Dintel_context_sseu.c18 const struct intel_sseu sseu) in gen8_emit_rpcs_config() argument
33 *cs++ = intel_sseu_make_rpcs(rq->engine->gt, &sseu); in gen8_emit_rpcs_config()
41 gen8_modify_rpcs(struct intel_context *ce, const struct intel_sseu sseu) in gen8_modify_rpcs() argument
66 ret = gen8_emit_rpcs_config(rq, ce, sseu); in gen8_modify_rpcs()
76 const struct intel_sseu sseu) in intel_context_reconfigure_sseu() argument
87 if (!memcmp(&ce->sseu, &sseu, sizeof(sseu))) in intel_context_reconfigure_sseu()
90 ret = gen8_modify_rpcs(ce, sseu); in intel_context_reconfigure_sseu()
92 ce->sseu = sseu; in intel_context_reconfigure_sseu()
H A Dintel_gt_mcr.h58 intel_sseu_has_subslice(&(gt_)->info.sseu, 0, ss_) : \
59 intel_sseu_has_subslice(&(gt_)->info.sseu, group_, instance_))
H A Dintel_workarounds.c546 if (!is_power_of_2(gt->info.sseu.subslice_7eu[i])) in skl_tune_iz_hashing()
555 ss = ffs(gt->info.sseu.subslice_7eu[i]) - 1; in skl_tune_iz_hashing()
1117 const struct sseu_dev_info *sseu = &to_gt(i915)->info.sseu; in gen9_wa_init_mcr() local
1134 slice = ffs(sseu->slice_mask) - 1; in gen9_wa_init_mcr()
1135 GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask.hsw)); in gen9_wa_init_mcr()
1136 subslice = ffs(intel_sseu_get_hsw_subslices(sseu, slice)); in gen9_wa_init_mcr()
1279 const struct sseu_dev_info *sseu = &gt->info.sseu; in icl_wa_init_mcr() local
1283 GEM_BUG_ON(hweight8(sseu->slice_mask) > 1); in icl_wa_init_mcr()
1294 subslice = __ffs(intel_sseu_get_hsw_subslices(sseu, 0)); in icl_wa_init_mcr()
1310 const struct sseu_dev_info *sseu = &gt->info.sseu; in xehp_init_mcr() local
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H A Dintel_gt_types.h275 struct sseu_dev_info sseu; member
H A Dintel_context_types.h180 struct intel_sseu sseu; member
H A Dintel_gt_mcr.c122 intel_slicemask_from_xehp_dssmask(gt->info.sseu.subslice_mask, in intel_gt_mcr_init()
622 dss = intel_sseu_find_first_xehp_dss(&gt->info.sseu, 0, 0); in get_nonterminated_steering()
H A Dintel_context.c401 ce->sseu = engine->sseu; in intel_context_init()
H A Dintel_context.h48 const struct intel_sseu sseu);
H A Dintel_engine_types.h420 struct intel_sseu sseu; member
H A Dintel_engine_cs.c820 int ss_per_ccs = info->sseu.max_subslices / I915_MAX_CCS; in engine_mask_apply_compute_fuses()
830 ccs_mask = intel_slicemask_from_xehp_dssmask(info->sseu.compute_subslice_mask, in engine_mask_apply_compute_fuses()
1281 engine->sseu = in engine_setup_common()
1282 intel_sseu_from_device_info(&engine->gt->info.sseu); in engine_setup_common()
H A Dintel_gt.c995 intel_sseu_dump(&info->sseu, p); in intel_gt_info_print()
H A Dintel_lrc.c1554 intel_sseu_make_rpcs(engine->gt, &ce->sseu); in lrc_update_regs()
H A Dintel_rps.c1287 switch (gt->info.sseu.eu_total) { in chv_rps_max_freq()
/linux-6.15/drivers/gpu/drm/i915/
H A Di915_query.c44 if (sseu->max_slices == 0) in fill_topology_info()
49 eu_length = sseu->max_slices * sseu->max_subslices * eu_stride; in fill_topology_info()
59 topo.max_slices = sseu->max_slices; in fill_topology_info()
73 &sseu->slice_mask, slice_length)) in fill_topology_info()
78 sseu)) in fill_topology_info()
84 sseu)) in fill_topology_info()
93 const struct sseu_dev_info *sseu = &to_gt(dev_priv)->info.sseu; in query_topology_info() local
98 return fill_topology_info(sseu, query_item, sseu->subslice_mask); in query_topology_info()
104 const struct sseu_dev_info *sseu; in query_geometry_subslices() local
122 sseu = &engine->gt->info.sseu; in query_geometry_subslices()
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H A Di915_getparam.c21 const struct sseu_dev_info *sseu = &to_gt(i915)->info.sseu; in i915_getparam_ioctl() local
79 value = intel_sseu_subslice_total(sseu); in i915_getparam_ioctl()
84 value = sseu->eu_total; in i915_getparam_ioctl()
101 value = sseu->min_eu_in_pool; in i915_getparam_ioctl()
173 value = sseu->slice_mask; in i915_getparam_ioctl()
183 value = intel_sseu_get_hsw_subslices(sseu, 0); in i915_getparam_ioctl()
H A Di915_perf_types.h445 struct intel_sseu sseu; member
H A Di915_perf.c381 struct intel_sseu sseu; member
2597 flex->value = intel_sseu_make_rpcs(ce->engine->gt, &ce->sseu); in gen8_configure_context()
2744 regs[0].value = intel_sseu_make_rpcs(engine->gt, &ce->sseu); in oa_configure_all_contexts()
3159 const struct sseu_dev_info *devinfo_sseu = &engine->gt->info.sseu; in get_default_sseu_config()
3351 stream->engine->gt->perf.sseu = props->sseu; in i915_oa_stream_init()
3859 get_default_sseu_config(&props->sseu, props->engine); in i915_perf_open_ioctl_locked()
4180 ret = get_sseu_config(&props->sseu, props->engine, &user_sseu); in read_properties_unlocked()
H A Di915_gpu_error.c726 intel_sseu_print_topology(gt->_gt->i915, &gt->info.sseu, &p); in err_print_gt_info()
/linux-6.15/drivers/gpu/drm/i915/gem/
H A Di915_gem_context.c821 struct intel_sseu *sseu; in set_proto_ctx_sseu() local
857 sseu = &pe->sseu; in set_proto_ctx_sseu()
867 sseu = &pc->legacy_rcs_sseu; in set_proto_ctx_sseu()
972 struct intel_sseu sseu) in intel_context_set_gem() argument
1003 ret = intel_context_reconfigure_sseu(ce, sseu); in intel_context_set_gem()
1129 struct intel_sseu sseu = {}; in default_engines() local
1148 sseu = rcs_sseu; in default_engines()
1150 ret = intel_context_set_gem(ce, ctx, sseu); in default_engines()
2013 struct intel_sseu sseu; in set_sseu() local
2051 ret = intel_context_reconfigure_sseu(ce, sseu); in set_sseu()
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H A Di915_gem_context_types.h125 struct intel_sseu sseu; member
/linux-6.15/drivers/gpu/drm/i915/gem/selftests/
H A Di915_gem_context.c1169 unsigned int slices = hweight32(ce->engine->sseu.slice_mask); in __sseu_finish()
1210 struct intel_sseu sseu) in __sseu_test() argument
1221 ret = intel_context_reconfigure_sseu(ce, sseu); in __sseu_test()
1226 hweight32(sseu.slice_mask), spin); in __sseu_test()
1271 if (hweight32(engine->sseu.slice_mask) < 2) in __igt_ctx_sseu()
1274 if (!engine->gt->info.sseu.has_slice_pg) in __igt_ctx_sseu()
1281 pg_sseu = engine->sseu; in __igt_ctx_sseu()
1284 ~(~0 << (hweight32(engine->sseu.subslice_mask) / 2)); in __igt_ctx_sseu()
1288 hweight32(engine->sseu.slice_mask), in __igt_ctx_sseu()
1302 ret = __sseu_test(name, flags, ce, obj, engine->sseu); in __igt_ctx_sseu()
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/linux-6.15/drivers/gpu/drm/i915/gt/uc/
H A Dintel_guc_ads.c900 hweight8(gt->info.sseu.slice_mask)); in __guc_ads_init()