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Searched refs:smu_wm_set (Results 1 – 12 of 12) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
H A Ddcn316_clk_mgr.c407 struct dcn316_watermarks *table = clk_mgr_dcn316->smu_wm_set.wm_set; in dcn316_notify_wm_ranges()
412 if (!table || clk_mgr_dcn316->smu_wm_set.mc_address.quad_part == 0) in dcn316_notify_wm_ranges()
420 clk_mgr_dcn316->smu_wm_set.mc_address.high_part); in dcn316_notify_wm_ranges()
422 clk_mgr_dcn316->smu_wm_set.mc_address.low_part); in dcn316_notify_wm_ranges()
604 &clk_mgr->smu_wm_set.mc_address.quad_part); in dcn316_clk_mgr_construct()
606 if (!clk_mgr->smu_wm_set.wm_set) { in dcn316_clk_mgr_construct()
607 clk_mgr->smu_wm_set.wm_set = &dummy_wms; in dcn316_clk_mgr_construct()
608 clk_mgr->smu_wm_set.mc_address.quad_part = 0; in dcn316_clk_mgr_construct()
610 ASSERT(clk_mgr->smu_wm_set.wm_set); in dcn316_clk_mgr_construct()
677 if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0) in dcn316_clk_mgr_destroy()
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H A Ddcn316_clk_mgr.h39 struct dcn316_smu_watermark_set smu_wm_set; member
/linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
H A Dvg_clk_mgr.c446 struct watermarks *table = clk_mgr_vgh->smu_wm_set.wm_set; in vg_notify_wm_ranges()
451 if (!table || clk_mgr_vgh->smu_wm_set.mc_address.quad_part == 0) in vg_notify_wm_ranges()
459 clk_mgr_vgh->smu_wm_set.mc_address.high_part); in vg_notify_wm_ranges()
461 clk_mgr_vgh->smu_wm_set.mc_address.low_part); in vg_notify_wm_ranges()
687 &clk_mgr->smu_wm_set.mc_address.quad_part); in vg_clk_mgr_construct()
689 if (!clk_mgr->smu_wm_set.wm_set) { in vg_clk_mgr_construct()
690 clk_mgr->smu_wm_set.wm_set = &dummy_wms; in vg_clk_mgr_construct()
691 clk_mgr->smu_wm_set.mc_address.quad_part = 0; in vg_clk_mgr_construct()
693 ASSERT(clk_mgr->smu_wm_set.wm_set); in vg_clk_mgr_construct()
750 if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0) in vg_clk_mgr_destroy()
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H A Dvg_clk_mgr.h42 struct smu_watermark_set smu_wm_set; member
/linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_clk_mgr.c481 struct dcn31_watermarks *table = clk_mgr_dcn31->smu_wm_set.wm_set; in dcn31_notify_wm_ranges()
486 if (!table || clk_mgr_dcn31->smu_wm_set.mc_address.quad_part == 0) in dcn31_notify_wm_ranges()
494 clk_mgr_dcn31->smu_wm_set.mc_address.high_part); in dcn31_notify_wm_ranges()
496 clk_mgr_dcn31->smu_wm_set.mc_address.low_part); in dcn31_notify_wm_ranges()
699 &clk_mgr->smu_wm_set.mc_address.quad_part); in dcn31_clk_mgr_construct()
701 if (!clk_mgr->smu_wm_set.wm_set) { in dcn31_clk_mgr_construct()
702 clk_mgr->smu_wm_set.wm_set = &dummy_wms; in dcn31_clk_mgr_construct()
703 clk_mgr->smu_wm_set.mc_address.quad_part = 0; in dcn31_clk_mgr_construct()
705 ASSERT(clk_mgr->smu_wm_set.wm_set); in dcn31_clk_mgr_construct()
806 if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0) in dcn31_clk_mgr_destroy()
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H A Ddcn31_clk_mgr.h39 struct dcn31_smu_watermark_set smu_wm_set; member
/linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/
H A Ddcn315_clk_mgr.c442 struct dcn315_watermarks *table = clk_mgr_dcn315->smu_wm_set.wm_set; in dcn315_notify_wm_ranges()
447 if (!table || clk_mgr_dcn315->smu_wm_set.mc_address.quad_part == 0) in dcn315_notify_wm_ranges()
455 clk_mgr_dcn315->smu_wm_set.mc_address.high_part); in dcn315_notify_wm_ranges()
457 clk_mgr_dcn315->smu_wm_set.mc_address.low_part); in dcn315_notify_wm_ranges()
630 &clk_mgr->smu_wm_set.mc_address.quad_part); in dcn315_clk_mgr_construct()
632 if (!clk_mgr->smu_wm_set.wm_set) { in dcn315_clk_mgr_construct()
633 clk_mgr->smu_wm_set.wm_set = &dummy_wms; in dcn315_clk_mgr_construct()
634 clk_mgr->smu_wm_set.mc_address.quad_part = 0; in dcn315_clk_mgr_construct()
636 ASSERT(clk_mgr->smu_wm_set.wm_set); in dcn315_clk_mgr_construct()
734 if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0) in dcn315_clk_mgr_destroy()
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H A Ddcn315_clk_mgr.h39 struct dcn315_smu_watermark_set smu_wm_set; member
/linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_clk_mgr.c545 struct dcn314_watermarks *table = clk_mgr_dcn314->smu_wm_set.wm_set; in dcn314_notify_wm_ranges()
550 if (!table || clk_mgr_dcn314->smu_wm_set.mc_address.quad_part == 0) in dcn314_notify_wm_ranges()
558 clk_mgr_dcn314->smu_wm_set.mc_address.high_part); in dcn314_notify_wm_ranges()
560 clk_mgr_dcn314->smu_wm_set.mc_address.low_part); in dcn314_notify_wm_ranges()
809 &clk_mgr->smu_wm_set.mc_address.quad_part); in dcn314_clk_mgr_construct()
811 if (!clk_mgr->smu_wm_set.wm_set) { in dcn314_clk_mgr_construct()
812 clk_mgr->smu_wm_set.wm_set = &dummy_wms; in dcn314_clk_mgr_construct()
813 clk_mgr->smu_wm_set.mc_address.quad_part = 0; in dcn314_clk_mgr_construct()
815 ASSERT(clk_mgr->smu_wm_set.wm_set); in dcn314_clk_mgr_construct()
916 if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0) in dcn314_clk_mgr_destroy()
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H A Ddcn314_clk_mgr.h42 struct dcn314_smu_watermark_set smu_wm_set; member
/linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
H A Ddcn35_clk_mgr.c800 struct dcn35_watermarks *table = clk_mgr_dcn35->smu_wm_set.wm_set; in dcn35_notify_wm_ranges()
805 if (!table || clk_mgr_dcn35->smu_wm_set.mc_address.quad_part == 0) in dcn35_notify_wm_ranges()
813 clk_mgr_dcn35->smu_wm_set.mc_address.high_part); in dcn35_notify_wm_ranges()
815 clk_mgr_dcn35->smu_wm_set.mc_address.low_part); in dcn35_notify_wm_ranges()
1275 &clk_mgr->smu_wm_set.mc_address.quad_part); in dcn35_clk_mgr_construct()
1277 if (!clk_mgr->smu_wm_set.wm_set) { in dcn35_clk_mgr_construct()
1278 clk_mgr->smu_wm_set.wm_set = &dummy_wms; in dcn35_clk_mgr_construct()
1279 clk_mgr->smu_wm_set.mc_address.quad_part = 0; in dcn35_clk_mgr_construct()
1281 ASSERT(clk_mgr->smu_wm_set.wm_set); in dcn35_clk_mgr_construct()
1430 if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0) in dcn35_clk_mgr_destroy()
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H A Ddcn35_clk_mgr.h46 struct dcn35_smu_watermark_set smu_wm_set; member