| /linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| H A D | dcn30_clk_mgr_smu_msg.c | 116 smu_print("SMU Test message: %d\n", input); in dcn30_smu_test_message()
128 smu_print("SMU Get SMU version\n"); in dcn30_smu_get_smu_version()
133 smu_print("SMU version: %d\n", *version); in dcn30_smu_get_smu_version()
146 smu_print("SMU Check driver if version\n"); in dcn30_smu_check_driver_if_version()
151 smu_print("SMU driver if version: %d\n", response); in dcn30_smu_check_driver_if_version()
165 smu_print("SMU Check msg header version\n"); in dcn30_smu_check_msg_header_version()
189 smu_print("SMU Set DRAM addr low: %d\n", addr_low); in dcn30_smu_set_dram_addr_low()
197 smu_print("SMU Transfer WM table SMU 2 DRAM\n"); in dcn30_smu_transfer_wm_table_smu_2_dram()
205 smu_print("SMU Transfer WM table DRAM 2 SMU\n"); in dcn30_smu_transfer_wm_table_dram_2_smu()
273 smu_print("SMU dpm freq: %d MHz\n", response); in dcn30_smu_get_dpm_freq_by_index()
[all …]
|
| /linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/ |
| H A D | dcn401_clk_mgr_smu_msg.c | 22 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); } macro
144 smu_print("FCLK P-state support value is : %d\n", support); in dcn401_smu_send_fclk_pstate_message()
152 smu_print("UCLK P-state support value is : %d\n", support); in dcn401_smu_send_uclk_pstate_message()
163 smu_print("Numways for SubVP : %d\n", num_ways); in dcn401_smu_send_cab_for_uclk_message()
168 smu_print("SMU Transfer WM table DRAM 2 SMU\n"); in dcn401_smu_transfer_wm_table_dram_2_smu()
176 smu_print("SMU Set PME workaround\n"); in dcn401_smu_set_pme_workaround()
216 smu_print("SMU Wait hard min status for %d us\n", total_delay_us); in dcn401_smu_wait_hard_min_status()
250 smu_print("SMU to wait for DMCUB ack for MCLK : %d\n", enable); in dcn401_smu_wait_for_dmub_ack_mclk()
257 smu_print("SMU Set indicate drr status = %d\n", mod_drr_for_pstate); in dcn401_smu_indicate_drr_status()
280 smu_print("SMU hard_min_done %d\n", success); in dcn401_smu_set_idle_uclk_fclk_hardmin()
[all …]
|
| /linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| H A D | dcn35_smu.c | 62 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); } macro
310 smu_print("%s smu_enable_phy_refclk_pwrdwn = %d\n", __func__, enable ? 1 : 0); in dcn35_smu_enable_phy_refclk_pwrdwn()
322 smu_print("%s: SMC_MSG_UpdatePmeRestore\n", __func__); in dcn35_smu_enable_pme_wa()
373 smu_print("%s: SMC_MSG_AllowZstatesEntry msg = ALLOW, param = 0x%x\n", __func__, param); in dcn35_smu_set_zstate_support()
379 smu_print("%s: SMC_MSG_AllowZstatesEntry msg_id = DISALLOW, param = 0x%x\n", __func__, param); in dcn35_smu_set_zstate_support()
412 smu_print("%s: msg_id = %d, param = 0x%x, return = 0x%x\n", __func__, msg_id, param, retv); in dcn35_smu_set_zstate_support()
426 smu_print("%s: SMU DPREF clk = %d mhz\n", __func__, dprefclk); in dcn35_smu_get_dprefclk()
441 smu_print("%s: get_dtbclk = %dmhz\n", __func__, dtbclk); in dcn35_smu_get_dtbclk()
454 smu_print("%s: smu_set_dtbclk = %d\n", __func__, enable ? 1 : 0); in dcn35_smu_set_dtbclk()
466 smu_print("%s: smu_enable_48mhz_tmdp_refclk_pwrdwn = %d\n", __func__, enable ? 1 : 0); in dcn35_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn()
[all …]
|
| /linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| H A D | dcn32_clk_mgr_smu_msg.c | 42 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); } macro
162 smu_print("FCLK P-state support value is : %d\n", enable); in dcn32_smu_send_fclk_pstate_message()
173 smu_print("Numways for SubVP : %d\n", num_ways); in dcn32_smu_send_cab_for_uclk_message()
178 smu_print("SMU Transfer WM table DRAM 2 SMU\n"); in dcn32_smu_transfer_wm_table_dram_2_smu()
186 smu_print("SMU Set PME workaround\n"); in dcn32_smu_set_pme_workaround()
219 smu_print("SMU Get hard min status: no_timeout %d delay %d us clk bits %x\n", in dcn32_smu_get_hard_min_status()
263 smu_print("SMU Wait get hard min status: %d timeouts\n", cur_wait_get_hard_min_max_timeouts); in dcn32_smu_wait_get_hard_min_status()
288 smu_print("SMU Set hard min by freq: clk = %d, freq_mhz = %d MHz\n", clk, freq_mhz); in dcn32_smu_set_hard_min_by_freq()
295 smu_print("SMU Frequency set = %d KHz hard_min_done %d\n", response, hard_min_done); in dcn32_smu_set_hard_min_by_freq()
297 smu_print("SMU Frequency set = %d KHz\n", response); in dcn32_smu_set_hard_min_by_freq()
[all …]
|
| /linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/ |
| H A D | dcn315_smu.c | 76 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); } macro
142 smu_print("SMU Response was not OK. SMU response after wait received is: %d\n", result); in dcn315_smu_send_msg_with_param()
165 smu_print("SMU msg id write fail %x times. \n", i + 1); in dcn315_smu_send_msg_with_param()
|
| /linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| H A D | rn_clk_mgr_vbios_smu.c | 50 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); } macro
108 smu_print("SMU Response was not OK. SMU response after wait received is: %d\n", result); in rn_vbios_smu_send_msg_with_param()
|
| /linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| H A D | dcn301_smu.c | 49 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); } macro
107 smu_print("SMU Response was not OK. SMU response after wait received is: %d\n", result); in dcn301_smu_send_msg_with_param()
|
| /linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
| H A D | dcn316_smu.c | 63 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); } macro
127 smu_print("SMU Response was not OK. SMU response after wait received is: %d\n", result); in dcn316_smu_send_msg_with_param()
|
| /linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| H A D | dcn314_smu.c | 62 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); } macro
128 smu_print("SMU Response was not OK. SMU response after wait received is: %d\n", in dcn314_smu_send_msg_with_param()
|
| /linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| H A D | dcn31_smu.c | 46 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); } macro
112 smu_print("SMU Response was not OK. SMU response after wait received is: %d\n", result); in dcn31_smu_send_msg_with_param()
|