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Searched refs:slices (Results 1 – 25 of 45) sorted by relevance

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/linux-6.15/block/partitions/
H A Dsysv68.c51 int i, slices; in sysv68_partition() local
68 slices = be16_to_cpu(b->dk_ios.ios_slccnt); in sysv68_partition()
76 slices -= 1; /* last slice is the whole disk */ in sysv68_partition()
77 snprintf(tmp, sizeof(tmp), "sysV68: %s(s%u)", state->name, slices); in sysv68_partition()
80 for (i = 0; i < slices; i++, slice++) { in sysv68_partition()
/linux-6.15/drivers/hte/
H A Dhte-tegra194.c120 u32 slices; member
326 .slices = 3,
335 .slices = 3,
342 .slices = 11,
349 .slices = 17,
689 u32 i, slices, val = 0; in tegra_hte_probe() local
711 slices = hte_dev->prov_data->slices; in tegra_hte_probe()
714 nlines = slices << 5; in tegra_hte_probe()
796 for (i = 0; i < slices; i++) { in tegra_hte_probe()
824 for (i = 0; i < slices; i++) { in tegra_hte_resume_early()
[all …]
/linux-6.15/Documentation/devicetree/bindings/timestamp/
H A Dnvidia,tegra194-hte.yaml17 a bitmap array arranged in 32bit slices where each bit represent signal/line
43 nvidia,slices:
50 GTE instances for both Tegra194 and Tegra234 has 3 slices. The Tegra194
51 LIC instance has 11 slices and Tegra234 LIC has 17 slices.
84 nvidia,slices:
95 nvidia,slices:
106 nvidia,slices:
/linux-6.15/drivers/phy/lantiq/
H A Dphy-lantiq-vrx200-pcie.c202 static const struct reg_default slices[] = { in ltq_vrx200_pcie_phy_apply_workarounds() local
218 for (i = 0; i < ARRAY_SIZE(slices); i++) { in ltq_vrx200_pcie_phy_apply_workarounds()
220 regmap_update_bits(priv->phy_regmap, slices[i].reg, in ltq_vrx200_pcie_phy_apply_workarounds()
221 slices[i].def, slices[i].def); in ltq_vrx200_pcie_phy_apply_workarounds()
226 regmap_update_bits(priv->phy_regmap, slices[i].reg, in ltq_vrx200_pcie_phy_apply_workarounds()
227 slices[i].def, 0x0); in ltq_vrx200_pcie_phy_apply_workarounds()
/linux-6.15/Documentation/admin-guide/perf/
H A Dqcom_l3_pmu.rst6 Centriq SoCs. The L3 cache on these SOCs is composed of multiple slices, shared
9 for aggregating across slices.
/linux-6.15/drivers/crypto/intel/qat/qat_common/
H A Dadf_admin.c334 struct icp_qat_fw_init_admin_slice_cnt *slices) in adf_send_admin_rl_init() argument
347 memcpy(slices, &resp.slices, sizeof(*slices)); in adf_send_admin_rl_init()
521 memcpy(slice_count, &resp.slices, sizeof(*slice_count)); in adf_send_admin_tl_start()
H A Dadf_admin.h18 struct icp_qat_fw_init_admin_slice_cnt *slices);
H A Dadf_rl.c565 avail_slice_cycles *= device_data->slices.pke_cnt; in adf_rl_calculate_slice_tokens()
568 avail_slice_cycles *= device_data->slices.cph_cnt; in adf_rl_calculate_slice_tokens()
571 avail_slice_cycles *= device_data->slices.dcpr_cnt; in adf_rl_calculate_slice_tokens()
623 sla_to_bytes *= device_data->slices.dcpr_cnt - in adf_rl_calculate_pci_bw()
1139 ret = adf_rl_send_admin_init_msg(accel_dev, &rl_hw_data->slices); in adf_rl_start()
H A Dadf_rl.h97 struct rl_slice_cnt slices; member
H A Dicp_qat_fw_init_admin.h160 struct icp_qat_fw_init_admin_slice_cnt slices; member
/linux-6.15/drivers/net/dsa/
H A Dbcm_sf2_cfp.c29 u8 slices[UDFS_PER_SLICE]; member
44 .slices = {
69 .slices = {
93 .slices = {
149 if (memcmp(slice_layout->slices, zero_slice, in bcm_sf2_get_slice_number()
165 core_writel(priv, layout->udfs[slice_num].slices[i], in bcm_sf2_cfp_udf_set()
410 num_udf = bcm_sf2_get_num_udf_slices(layout->udfs[slice_num].slices); in bcm_sf2_cfp_ipv4_rule_set()
668 num_udf = bcm_sf2_get_num_udf_slices(layout->udfs[slice_num].slices); in bcm_sf2_cfp_ipv6_rule_set()
774 num_udf = bcm_sf2_get_num_udf_slices(layout->udfs[slice_num].slices); in bcm_sf2_cfp_ipv6_rule_set()
/linux-6.15/Documentation/scheduler/
H A Dsched-eevdf.rst21 allows latency-sensitive tasks with shorter time slices to be prioritized,
31 can request specific time slices using the new sched_setattr() system call,
H A Dschedutil.rst15 individual tasks to task-group slices to CPU runqueues. As the basis for this
31 Note that blocked tasks still contribute to the aggregates (task-group slices
/linux-6.15/drivers/gpu/drm/i915/gt/
H A Dintel_sseu.c658 u8 slices, subslices; in intel_sseu_make_rpcs() local
675 slices = hweight8(req_sseu->slice_mask); in intel_sseu_make_rpcs()
704 slices == 1 && in intel_sseu_make_rpcs()
709 slices *= 2; in intel_sseu_make_rpcs()
719 u32 mask, val = slices; in intel_sseu_make_rpcs()
/linux-6.15/drivers/gpu/drm/i915/gem/selftests/
H A Di915_gem_context.c1137 __check_rpcs(const char *name, u32 rpcs, int slices, unsigned int expected, in __check_rpcs() argument
1140 if (slices == expected) in __check_rpcs()
1143 if (slices < 0) { in __check_rpcs()
1145 name, prefix, slices, suffix); in __check_rpcs()
1146 return slices; in __check_rpcs()
1150 name, prefix, slices, expected, suffix); in __check_rpcs()
1153 rpcs, slices, in __check_rpcs()
1169 unsigned int slices = hweight32(ce->engine->sseu.slice_mask); in __sseu_finish() local
1186 ret = __check_rpcs(name, rpcs, ret, slices, "Kernel context", "!"); in __sseu_finish()
/linux-6.15/drivers/gpu/drm/i915/display/
H A Dskl_watermark.c639 if (dbuf_state->slices[pipe] != dbuf_state->slices[for_pipe]) in intel_crtc_dbuf_weights()
692 if (old_dbuf_state->slices[pipe] == new_dbuf_state->slices[pipe] && in skl_crtc_allocate_ddb()
715 old_dbuf_state->slices[pipe], new_dbuf_state->slices[pipe], in skl_crtc_allocate_ddb()
2641 enabled_slices |= dbuf_state->slices[pipe]; in intel_dbuf_enabled_slices()
2692 new_dbuf_state->slices[pipe] = in skl_compute_ddb()
2696 if (old_dbuf_state->slices[pipe] == new_dbuf_state->slices[pipe]) in skl_compute_ddb()
3171 u8 slices; in skl_wm_get_hw_state() local
3217 dbuf_state->slices[pipe] = in skl_wm_get_hw_state()
3795 u8 slices; in skl_dbuf_is_misconfigured() local
3799 if (dbuf_state->slices[crtc->pipe] & ~slices) in skl_dbuf_is_misconfigured()
[all …]
H A Dskl_watermark.h71 u8 slices[I915_MAX_PIPES]; member
/linux-6.15/fs/bfs/
H A DKconfig13 to "UnixWare slices support", below. More information about the BFS
/linux-6.15/arch/arm64/kvm/
H A Dguest.c654 const unsigned int slices = vcpu_sve_slices(vcpu); in num_sve_regs() local
662 return slices * (SVE_NUM_PREGS + SVE_NUM_ZREGS + 1 /* FFR */) in num_sve_regs()
669 const unsigned int slices = vcpu_sve_slices(vcpu); in copy_sve_reg_indices() local
689 for (i = 0; i < slices; i++) { in copy_sve_reg_indices()
/linux-6.15/drivers/usb/dwc2/
H A Dhcd_queue.c521 int slices = DIV_ROUND_UP(qh->device_us, DWC2_US_PER_SLICE); in dwc2_ls_pmap_schedule() local
541 DWC2_LS_SCHEDULE_FRAMES, slices, in dwc2_ls_pmap_schedule()
560 int slices = DIV_ROUND_UP(qh->device_us, DWC2_US_PER_SLICE); in dwc2_ls_pmap_unschedule() local
568 DWC2_LS_SCHEDULE_FRAMES, slices, qh->device_interval, in dwc2_ls_pmap_unschedule()
/linux-6.15/Documentation/filesystems/
H A Dbfs.rst12 know the partition number and the kernel must support UnixWare disk slices
/linux-6.15/drivers/accel/qaic/
H A Dqaic.h195 struct list_head slices; member
H A Dqaic_data.c428 list_add_tail(&slice->slice, &bo->slices); in qaic_map_one_slice()
663 INIT_LIST_HEAD(&bo->slices); in qaic_init_bo()
911 list_for_each_entry_safe(slice, temp, &bo->slices, slice) in qaic_free_slices_bo()
1220 list_for_each_entry(slice, &bo->slices, slice) { in send_bo_list_to_device()
/linux-6.15/tools/perf/Documentation/
H A Dperf-diff.txt142 Select the first and the second 10% time slices to diff:
146 Select from 0% to 10% and 30% to 40% slices to diff:
/linux-6.15/tools/sched_ext/
H A DREADME.md186 single CPU, allowing other cores to run with infinite slices, without timer
192 infinite slices and no timer ticks allows the VM to avoid unnecessary expensive

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