| /linux-6.15/drivers/pci/controller/dwc/ |
| H A D | pcie-amd-mdb.c | 63 void __iomem *slcr; member
88 writel_relaxed(val, pcie->slcr + AMD_MDB_TLP_IR_DISABLE_MISC); in amd_mdb_intx_irq_mask()
108 writel_relaxed(val, pcie->slcr + AMD_MDB_TLP_IR_ENABLE_MISC); in amd_mdb_intx_irq_unmask()
148 val = readl_relaxed(pcie->slcr + AMD_MDB_TLP_IR_STATUS_MISC); in dw_pcie_rp_intx()
197 writel_relaxed(val, pcie->slcr + AMD_MDB_TLP_IR_ENABLE_MISC); in amd_mdb_event_irq_unmask()
228 val = readl_relaxed(pcie->slcr + AMD_MDB_TLP_IR_STATUS_MISC); in amd_mdb_pcie_event()
229 val &= ~readl_relaxed(pcie->slcr + AMD_MDB_TLP_IR_MASK_MISC); in amd_mdb_pcie_event()
256 pcie->slcr + AMD_MDB_TLP_IR_DISABLE_MISC); in amd_mdb_pcie_init_port()
265 pcie->slcr + AMD_MDB_TLP_IR_ENABLE_MISC); in amd_mdb_pcie_init_port()
414 if (IS_ERR(pcie->slcr)) in amd_mdb_add_pcie_port()
[all …]
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| /linux-6.15/drivers/reset/ |
| H A D | reset-zynq.c | 21 struct regmap *slcr; member
40 return regmap_update_bits(priv->slcr, in zynq_reset_assert()
57 return regmap_update_bits(priv->slcr, in zynq_reset_deassert()
76 ret = regmap_read(priv->slcr, priv->offset + (bank * 4), ®); in zynq_reset_status()
98 priv->slcr = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, in zynq_reset_probe()
100 if (IS_ERR(priv->slcr)) { in zynq_reset_probe()
102 return PTR_ERR(priv->slcr); in zynq_reset_probe()
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| /linux-6.15/drivers/fpga/ |
| H A D | zynq-fpga.c | 127 struct regmap *slcr; member
286 regmap_write(priv->slcr, SLCR_FPGA_RST_CTRL_OFFSET, in zynq_fpga_ops_write_init()
290 regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET, in zynq_fpga_ops_write_init()
293 regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET, in zynq_fpga_ops_write_init()
513 regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET, in zynq_fpga_ops_write_complete()
517 regmap_write(priv->slcr, SLCR_FPGA_RST_CTRL_OFFSET, in zynq_fpga_ops_write_complete()
569 priv->slcr = syscon_regmap_lookup_by_phandle(dev->of_node, in zynq_fpga_probe()
571 if (IS_ERR(priv->slcr)) { in zynq_fpga_probe()
573 return PTR_ERR(priv->slcr); in zynq_fpga_probe()
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| /linux-6.15/Documentation/devicetree/bindings/reset/ |
| H A D | zynq-reset.txt | 10 - syscon: <&slcr>
21 syscon = <&slcr>;
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| /linux-6.15/arch/arm/boot/dts/xilinx/ |
| H A D | zynq-7000.dtsi | 334 slcr: slcr@f8000000 { label
338 compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
364 syscon = <&slcr>;
370 syscon = <&slcr>;
399 syscon = <&slcr>;
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| /linux-6.15/drivers/clk/zynq/ |
| H A D | clkc.c | 580 struct device_node *slcr; in zynq_clock_init() local
594 slcr = of_get_parent(np); in zynq_clock_init()
596 if (slcr->data) { in zynq_clock_init()
597 zynq_clkc_base = (__force void __iomem *)slcr->data + res.start; in zynq_clock_init()
600 of_node_put(slcr); in zynq_clock_init()
606 of_node_put(slcr); in zynq_clock_init()
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| /linux-6.15/arch/arm/mach-zynq/ |
| H A D | Makefile | 7 obj-y := common.o slcr.o pm.o
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| /linux-6.15/Documentation/devicetree/bindings/pci/ |
| H A D | amd,versal2-mdb-host.yaml | 29 - const: slcr
100 reg-names = "slcr", "config", "dbi", "atu";
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| H A D | snps,dw-pcie.yaml | 117 const: slcr
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| /linux-6.15/Documentation/devicetree/bindings/fpga/ |
| H A D | xilinx-zynq-fpga-mgr.yaml | 51 syscon = <&slcr>;
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| /linux-6.15/Documentation/devicetree/bindings/pinctrl/ |
| H A D | xlnx,pinctrl-zynq.yaml | 186 syscon = <&slcr>;
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| /linux-6.15/drivers/net/ethernet/mellanox/mlxsw/ |
| H A D | reg.h | 1301 MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN);
1315 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1);
1324 MLXSW_ITEM32_LP(reg, slcr, 0x00, 16, 0x00, 12);
1336 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4);
1396 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20);
1402 MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32);
1406 MLXSW_REG_ZERO(slcr, payload); in mlxsw_reg_slcr_pack()
13016 MLXSW_REG(slcr),
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| H A D | spectrum.c | 2641 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl); in mlxsw_sp_lag_init()
|