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Searched refs:skl (Results 1 – 18 of 18) sorted by relevance

/linux-6.15/drivers/gpu/drm/i915/display/
H A Dskl_watermark.c1561 memset(crtc_state->wm.skl.plane_ddb, 0, sizeof(crtc_state->wm.skl.plane_ddb)); in skl_crtc_allocate_plane_ddb()
1562 memset(crtc_state->wm.skl.plane_ddb_y, 0, sizeof(crtc_state->wm.skl.plane_ddb_y)); in skl_crtc_allocate_plane_ddb()
1636 &crtc_state->wm.skl.plane_ddb[plane_id]; in skl_crtc_allocate_plane_ddb()
1703 &crtc_state->wm.skl.plane_ddb[plane_id]; in skl_crtc_allocate_plane_ddb()
2519 crtc_state->wm.skl.optimal = crtc_state->wm.skl.raw; in skl_build_pipe_wm()
2969 &old_crtc_state->wm.skl.optimal, in skl_wm_add_affected_planes()
2970 &new_crtc_state->wm.skl.optimal)) in skl_wm_add_affected_planes()
3173 memset(&crtc_state->wm.skl.optimal, 0, in skl_wm_get_hw_state()
3179 crtc_state->wm.skl.raw = crtc_state->wm.skl.optimal; in skl_wm_get_hw_state()
3842 memset(&crtc_state->wm.skl.ddb, 0, sizeof(crtc_state->wm.skl.ddb)); in skl_dbuf_sanitize()
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H A Dintel_atomic_plane.c794 if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb[plane_id], in skl_next_plane_to_commit()
796 skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_y[plane_id], in skl_next_plane_to_commit()
801 ddb[plane_id] = crtc_state->wm.skl.plane_ddb[plane_id]; in skl_next_plane_to_commit()
802 ddb_y[plane_id] = crtc_state->wm.skl.plane_ddb_y[plane_id]; in skl_next_plane_to_commit()
911 memcpy(ddb, old_crtc_state->wm.skl.plane_ddb, in skl_crtc_planes_update_arm()
912 sizeof(old_crtc_state->wm.skl.plane_ddb)); in skl_crtc_planes_update_arm()
913 memcpy(ddb_y, old_crtc_state->wm.skl.plane_ddb_y, in skl_crtc_planes_update_arm()
914 sizeof(old_crtc_state->wm.skl.plane_ddb_y)); in skl_crtc_planes_update_arm()
H A Dintel_dpll_mgr.h274 struct skl_dpll_hw_state skl; member
H A Dintel_dpll_mgr.c1384 const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; in skl_ddi_pll_enable()
1406 const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; in skl_ddi_dpll0_enable()
1431 struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; in skl_ddi_pll_get_hw_state()
1469 struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; in skl_ddi_dpll0_get_hw_state()
1742 const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; in skl_ddi_wrpll_get_freq()
1813 struct skl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.skl; in skl_ddi_hdmi_pll_dividers()
1890 const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; in skl_ddi_lcpll_get_freq()
1969 const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; in skl_ddi_pll_get_freq()
1990 const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; in skl_dump_hw_state()
1999 const struct skl_dpll_hw_state *a = &_a->skl; in skl_compare_hw_state()
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H A Dskl_universal_plane.c833 const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal; in skl_write_plane_wm()
835 &crtc_state->wm.skl.plane_ddb[plane_id]; in skl_write_plane_wm()
837 &crtc_state->wm.skl.plane_ddb_y[plane_id]; in skl_write_plane_wm()
838 const u16 *min_ddb = &crtc_state->wm.skl.plane_min_ddb[plane_id]; in skl_write_plane_wm()
840 &crtc_state->wm.skl.plane_interim_ddb[plane_id]; in skl_write_plane_wm()
H A Dintel_cursor.c633 const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal; in skl_write_cursor_wm()
635 &crtc_state->wm.skl.plane_ddb[plane_id]; in skl_write_cursor_wm()
H A Dintel_display_debugfs.c673 entry = &crtc_state->wm.skl.plane_ddb[plane_id]; in i915_ddb_info()
679 entry = &crtc_state->wm.skl.plane_ddb[PLANE_CURSOR]; in i915_ddb_info()
H A Dintel_bw.c1203 &crtc_state->wm.skl.plane_ddb[plane_id], in skl_crtc_calc_dbuf_bw()
1208 &crtc_state->wm.skl.plane_ddb_y[plane_id], in skl_crtc_calc_dbuf_bw()
H A Dintel_display.c6898 entries[pipe] = old_crtc_state->wm.skl.ddb; in skl_commit_modeset_enables()
6937 if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, in skl_commit_modeset_enables()
6941 entries[pipe] = new_crtc_state->wm.skl.ddb; in skl_commit_modeset_enables()
6952 if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb, in skl_commit_modeset_enables()
6953 &old_crtc_state->wm.skl.ddb) && in skl_commit_modeset_enables()
7026 skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, in skl_commit_modeset_enables()
7029 entries[pipe] = new_crtc_state->wm.skl.ddb; in skl_commit_modeset_enables()
H A Dintel_dmc.c160 #define SKL_DMC_PATH DMC_LEGACY_PATH(skl, 1, 27)
H A Dintel_display_types.h888 } skl; member
/linux-6.15/sound/soc/sof/intel/
H A DMakefile34 snd-sof-pci-intel-skl-y := pci-skl.o skl.o hda-loader-skl.o
44 obj-$(CONFIG_SND_SOC_SOF_INTEL_SKL) += snd-sof-pci-intel-skl.o
/linux-6.15/sound/soc/intel/avs/
H A DMakefile7 snd-soc-avs-y += skl.o apl.o cnl.o icl.o tgl.o
H A Dskl.c178 AVS_SET_ENABLE_LOGS_OP(skl)
/linux-6.15/sound/soc/intel/common/
H A DMakefile4 soc-acpi-intel-skl-match.o soc-acpi-intel-kbl-match.o \
/linux-6.15/drivers/platform/x86/intel/int3472/
H A DKconfig31 The module will be named "intel-skl-int3472".
/linux-6.15/drivers/gpu/drm/i915/
H A Dintel_clock_gating.c717 CG_FUNCS(skl);
/linux-6.15/drivers/gpu/drm/i915/gt/uc/
H A Dintel_uc_fw.c111 fw_def(SKYLAKE, 0, guc_mmp(skl, 70, 1, 1))
132 fw_def(SKYLAKE, 0, huc_mmp(skl, 2, 0, 0))