Home
last modified time | relevance | path

Searched refs:simd (Results 1 – 19 of 19) sorted by relevance

/linux-6.15/crypto/
H A Dsimd.c215 struct simd_skcipher_alg *simd; in simd_register_skciphers_compat() local
227 simd = simd_skcipher_create_compat(algs + i, algname, drvname, basename); in simd_register_skciphers_compat()
228 err = PTR_ERR(simd); in simd_register_skciphers_compat()
229 if (IS_ERR(simd)) in simd_register_skciphers_compat()
231 simd_algs[i] = simd; in simd_register_skciphers_compat()
438 struct simd_aead_alg *simd; in simd_register_aeads_compat() local
450 simd = simd_aead_create_compat(algs + i, algname, drvname, basename); in simd_register_aeads_compat()
451 err = PTR_ERR(simd); in simd_register_aeads_compat()
452 if (IS_ERR(simd)) in simd_register_aeads_compat()
454 simd_algs[i] = simd; in simd_register_aeads_compat()
H A DMakefile207 crypto_simd-y := simd.o
/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_4_2.c422 uint32_t se, cu, simd, wave; in gfx_v9_4_2_log_wave_assignment() local
437 for (simd = 0; simd < SIMD_ID_MAX; simd++) { in gfx_v9_4_2_log_wave_assignment()
456 uint32_t se, cu, simd, wave; in gfx_v9_4_2_wait_for_waves_assigned() local
467 for (simd = 0; simd < SIMD_ID_MAX; simd++) in gfx_v9_4_2_wait_for_waves_assigned()
1808 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_ind()
1818 uint32_t i, simd, wave; in gfx_v9_4_2_log_cu_timeout_status() local
1829 simd = i / cu_info->max_waves_per_simd; in gfx_v9_4_2_log_cu_timeout_status()
1836 wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v9_4_2_log_cu_timeout_status()
1838 wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v9_4_2_log_cu_timeout_status()
1840 wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); in gfx_v9_4_2_log_cu_timeout_status()
[all …]
H A Dgfx_v6_0.c2964 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_ind()
2970 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, in wave_read_regs() argument
2976 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_regs()
2989 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v6_0_read_wave_data()
2990 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v6_0_read_wave_data()
2991 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v6_0_read_wave_data()
2994 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); in gfx_v6_0_read_wave_data()
3000 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); in gfx_v6_0_read_wave_data()
3006 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); in gfx_v6_0_read_wave_data()
3007 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE); in gfx_v6_0_read_wave_data()
[all …]
H A Damdgpu_umr.h50 u32 gpr_or_wave, se, sh, cu, wave, simd, xcc_id; member
H A Dgfx_v7_0.c4059 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_ind()
4065 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, in wave_read_regs() argument
4071 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_regs()
4084 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v7_0_read_wave_data()
4085 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v7_0_read_wave_data()
4086 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v7_0_read_wave_data()
4089 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); in gfx_v7_0_read_wave_data()
4095 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); in gfx_v7_0_read_wave_data()
4101 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); in gfx_v7_0_read_wave_data()
4102 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE); in gfx_v7_0_read_wave_data()
[all …]
H A Damdgpu_debugfs.c434 adev->gfx.funcs->read_wave_data(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, data, &x); in amdgpu_debugfs_gprwave_read()
439 …adev->gfx.funcs->read_wave_vgprs(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, rd->id.gpr.thread,… in amdgpu_debugfs_gprwave_read()
442 …adev->gfx.funcs->read_wave_sgprs(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, *pos, size>>2, dat… in amdgpu_debugfs_gprwave_read()
1061 uint32_t offset, se, sh, cu, wave, simd, data[32]; in amdgpu_debugfs_wave_read() local
1072 simd = (*pos & GENMASK_ULL(44, 37)) >> 37; in amdgpu_debugfs_wave_read()
1092 adev->gfx.funcs->read_wave_data(adev, 0, simd, wave, data, &x); in amdgpu_debugfs_wave_read()
1153 uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data; in amdgpu_debugfs_gpr_read() local
1164 simd = (*pos & GENMASK_ULL(51, 44)) >> 44; in amdgpu_debugfs_gpr_read()
1186 adev->gfx.funcs->read_wave_vgprs(adev, 0, simd, wave, thread, offset, size>>2, data); in amdgpu_debugfs_gpr_read()
1189 adev->gfx.funcs->read_wave_sgprs(adev, 0, simd, wave, offset, size>>2, data); in amdgpu_debugfs_gpr_read()
H A Dgfx_v9_4_3.c715 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_ind()
727 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_regs()
737 uint32_t xcc_id, uint32_t simd, uint32_t wave, in gfx_v9_4_3_read_wave_data() argument
742 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS); in gfx_v9_4_3_read_wave_data()
743 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v9_4_3_read_wave_data()
744 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v9_4_3_read_wave_data()
747 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_HW_ID); in gfx_v9_4_3_read_wave_data()
755 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_M0); in gfx_v9_4_3_read_wave_data()
756 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_MODE); in gfx_v9_4_3_read_wave_data()
763 wave_read_regs(adev, xcc_id, simd, wave, 0, in gfx_v9_4_3_read_wave_sgprs()
[all …]
H A Damdgpu_gfx.h295 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
297 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
300 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
H A Dgfx_v8_0.c5180 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_ind()
5186 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, in wave_read_regs() argument
5192 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_regs()
5205 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v8_0_read_wave_data()
5206 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v8_0_read_wave_data()
5207 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v8_0_read_wave_data()
5210 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); in gfx_v8_0_read_wave_data()
5216 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); in gfx_v8_0_read_wave_data()
5222 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); in gfx_v8_0_read_wave_data()
5223 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE); in gfx_v8_0_read_wave_data()
[all …]
H A Dgfx_v9_0.c1933 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_ind()
1939 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, in wave_read_regs() argument
1945 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_regs()
1958 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v9_0_read_wave_data()
1959 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v9_0_read_wave_data()
1960 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v9_0_read_wave_data()
1963 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); in gfx_v9_0_read_wave_data()
1971 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); in gfx_v9_0_read_wave_data()
1972 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE); in gfx_v9_0_read_wave_data()
1980 adev, simd, wave, 0, in gfx_v9_0_read_wave_sgprs()
[all …]
H A Dgfx_v12_0.c820 uint32_t simd, uint32_t wave, in gfx_v12_0_read_wave_data() argument
826 WARN_ON(simd != 0); in gfx_v12_0_read_wave_data()
856 uint32_t xcc_id, uint32_t simd, in gfx_v12_0_read_wave_sgprs() argument
860 WARN_ON(simd != 0); in gfx_v12_0_read_wave_sgprs()
868 uint32_t xcc_id, uint32_t simd, in gfx_v12_0_read_wave_vgprs() argument
H A Dgfx_v11_0.c1000 static void gfx_v11_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, ui… in gfx_v11_0_read_wave_data() argument
1005 WARN_ON(simd != 0); in gfx_v11_0_read_wave_data()
1026 static void gfx_v11_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, in gfx_v11_0_read_wave_sgprs() argument
1030 WARN_ON(simd != 0); in gfx_v11_0_read_wave_sgprs()
1037 static void gfx_v11_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, in gfx_v11_0_read_wave_vgprs() argument
H A Dgfx_v10_0.c4496 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, ui… in gfx_v10_0_read_wave_data() argument
4502 WARN_ON(simd != 0); in gfx_v10_0_read_wave_data()
4524 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, in gfx_v10_0_read_wave_sgprs() argument
4528 WARN_ON(simd != 0); in gfx_v10_0_read_wave_sgprs()
4535 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, in gfx_v10_0_read_wave_vgprs() argument
/linux-6.15/arch/arm/crypto/
H A Daes-neonbs-glue.c473 struct simd_skcipher_alg *simd; in aes_init() local
494 simd = simd_skcipher_create_compat(aes_algs + i, algname, drvname, basename); in aes_init()
495 err = PTR_ERR(simd); in aes_init()
496 if (IS_ERR(simd)) in aes_init()
499 aes_simd_algs[i] = simd; in aes_init()
H A Daes-ce-glue.c696 struct simd_skcipher_alg *simd; in aes_init() local
714 simd = simd_skcipher_create_compat(aes_algs + i, algname, drvname, basename); in aes_init()
715 err = PTR_ERR(simd); in aes_init()
716 if (IS_ERR(simd)) in aes_init()
719 aes_simd_algs[i] = simd; in aes_init()
/linux-6.15/lib/crypto/
H A DMakefile62 obj-$(CONFIG_CRYPTO_MANAGER_EXTRA_TESTS) += simd.o
/linux-6.15/include/asm-generic/
H A DKbuild54 mandatory-y += simd.h
/linux-6.15/tools/perf/Documentation/
H A Dperf-report.txt138 …- simd: Flags describing a SIMD operation. "e" for empty Arm SVE predicate. "p" for partial Arm SV…