Searched refs:sel_mux_phy_c_d_phy_f_g (Results 1 – 2 of 2) sorted by relevance
381 boot_options.bits.sel_mux_phy_c_d_phy_f_g = (dmub->asic == DMUB_ASIC_DCN31B) ? 1 : 0; in dmub_dcn31_enable_dmub_boot_options()
764 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled on DCN31 */ member