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Searched refs:sdhci_readl (Results 1 – 25 of 26) sorted by relevance

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/linux-6.15/drivers/mmc/host/
H A Dsdhci-xenon-phy.c256 reg = sdhci_readl(host, phy_regs->timing_adj); in xenon_emmc_phy_init()
295 ret = read_poll_timeout(sdhci_readl, reg, in xenon_emmc_phy_init()
361 reg = sdhci_readl(host, phy_regs->dll_ctrl); in xenon_emmc_phy_enable_dll()
366 reg = sdhci_readl(host, phy_regs->dll_ctrl); in xenon_emmc_phy_enable_dll()
450 reg = sdhci_readl(host, XENON_SLOT_EMMC_CTRL); in xenon_emmc_phy_disable_strobe()
484 reg = sdhci_readl(host, XENON_SLOT_EMMC_CTRL); in xenon_emmc_phy_strobe_delay_adj()
586 reg = sdhci_readl(host, phy_regs->pad_ctrl); in xenon_emmc_phy_set()
630 reg = sdhci_readl(host, phy_regs->pad_ctrl2); in xenon_emmc_phy_set()
639 reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL); in xenon_emmc_phy_set()
643 reg = sdhci_readl(host, phy_regs->func_ctrl); in xenon_emmc_phy_set()
[all …]
H A Dsdhci-of-esdhc.c851 val = sdhci_readl(host, ESDHC_TBCTL); in esdhc_reset()
901 val = sdhci_readl(host, ESDHC_PROCTL); in esdhc_signal_voltage_switch()
963 val = sdhci_readl(host, ESDHC_TBCTL); in esdhc_tuning_block_enable()
979 val = sdhci_readl(host, ESDHC_TBCTL); in esdhc_tuning_window_ptr()
987 val = sdhci_readl(host, ESDHC_TBCTL); in esdhc_tuning_window_ptr()
993 val = sdhci_readl(host, ESDHC_TBSTAT); in esdhc_tuning_window_ptr()
994 val = sdhci_readl(host, ESDHC_TBSTAT); in esdhc_tuning_window_ptr()
1051 val = sdhci_readl(host, ESDHC_TBCTL); in esdhc_execute_sw_tuning()
1101 val = sdhci_readl(host, ESDHC_TBCTL); in esdhc_execute_tuning()
1184 val = sdhci_readl(host, ESDHC_TBCTL); in esdhc_set_uhs_signaling()
[all …]
H A Dsdhci_f_sdh30.c45 ctrl = sdhci_readl(host, F_SDH30_IO_CONTROL2); in sdhci_f_sdh30_soft_voltage_switch()
57 ctrl = sdhci_readl(host, F_SDH30_ESD_CONTROL); in sdhci_f_sdh30_soft_voltage_switch()
62 ctrl = sdhci_readl(host, F_SDH30_TUNING_SETTING); in sdhci_f_sdh30_soft_voltage_switch()
83 ctl = sdhci_readl(host, F_SDH30_ESD_CONTROL); in sdhci_f_sdh30_reset()
89 !(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) { in sdhci_f_sdh30_reset()
90 ctl = sdhci_readl(host, F_SDH30_TEST); in sdhci_f_sdh30_reset()
179 reg = sdhci_readl(host, F_SDH30_ESD_CONTROL); in sdhci_f_sdh30_probe()
184 reg = sdhci_readl(host, SDHCI_CAPABILITIES); in sdhci_f_sdh30_probe()
H A Dsdhci-xenon.c32 reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL); in xenon_enable_internal_clk()
60 reg = sdhci_readl(host, XENON_SYS_OP_CTRL); in xenon_set_sdclk_off_idle()
76 reg = sdhci_readl(host, XENON_SYS_OP_CTRL); in xenon_set_acg()
90 reg = sdhci_readl(host, XENON_SYS_OP_CTRL); in xenon_enable_sdhc()
108 reg = sdhci_readl(host, XENON_SYS_OP_CTRL); in xenon_disable_sdhc()
119 reg = sdhci_readl(host, XENON_SYS_EXT_OP_CTRL); in xenon_enable_sdhc_parallel_tran()
129 reg = sdhci_readl(host, XENON_SYS_EXT_OP_CTRL); in xenon_mask_cmd_conflict_err()
146 reg = sdhci_readl(host, SDHCI_SIGNAL_ENABLE); in xenon_retune_setup()
149 reg = sdhci_readl(host, SDHCI_INT_ENABLE); in xenon_retune_setup()
391 reg = sdhci_readl(host, XENON_SYS_CFG_INFO); in xenon_enable_sdio_irq()
[all …]
H A Dsdhci-bcm-kona.c56 val = sdhci_readl(host, KONA_SDHOST_CORECTRL); in sdhci_bcm_kona_sd_reset()
60 while (!(sdhci_readl(host, KONA_SDHOST_CORECTRL) & KONA_SDHOST_RESET)) { in sdhci_bcm_kona_sd_reset()
68 val = sdhci_readl(host, KONA_SDHOST_CORECTRL); in sdhci_bcm_kona_sd_reset()
88 val = sdhci_readl(host, KONA_SDHOST_COREIMR); in sdhci_bcm_kona_sd_init()
93 val = sdhci_readl(host, KONA_SDHOST_CORECTRL); in sdhci_bcm_kona_sd_init()
127 val = sdhci_readl(host, KONA_SDHOST_CORESTAT); in sdhci_bcm_kona_sd_card_emulate()
H A Dsdhci-pci-dwc-mshc.c39 reg = sdhci_readl(host, (SDHC_AT_CTRL_R + vendor_ptr)); in sdhci_snps_set_clock()
47 reg = sdhci_readl(host, (SDHC_GPIO_OUT + vendor_ptr)); in sdhci_snps_set_clock()
63 reg = sdhci_readl(host, (SDHC_GPIO_OUT + vendor_ptr)); in sdhci_snps_set_clock()
H A Dsdhci-milbeaut.c65 ctrl = sdhci_readl(host, F_SDH30_IO_CONTROL2); in sdhci_milbeaut_soft_voltage_switch()
75 ctrl = sdhci_readl(host, F_SDH30_TUNING_SETTING); in sdhci_milbeaut_soft_voltage_switch()
118 ctl = sdhci_readl(host, F_SDH30_ESD_CONTROL); in sdhci_milbeaut_reset()
149 val = sdhci_readl(host, MLB_CR_SET); in sdhci_milbeaut_bridge_init()
181 ctl = sdhci_readl(host, F_SDH30_IO_CONTROL2); in sdhci_milbeaut_vendor_init()
196 ctl = sdhci_readl(host, F_SDH30_ESD_CONTROL); in sdhci_milbeaut_vendor_init()
H A Dsdhci-uhs2.c45 sdhci_readl(host, SDHCI_UHS2_BLOCK_COUNT)); in sdhci_uhs2_dump_regs()
58 sdhci_readl(host, SDHCI_UHS2_INT_STATUS), in sdhci_uhs2_dump_regs()
59 sdhci_readl(host, SDHCI_UHS2_INT_STATUS_ENABLE)); in sdhci_uhs2_dump_regs()
61 sdhci_readl(host, SDHCI_UHS2_INT_SIGNAL_ENABLE)); in sdhci_uhs2_dump_regs()
248 ier = sdhci_readl(host, SDHCI_UHS2_INT_STATUS_ENABLE); in sdhci_uhs2_clear_set_irqs()
372 caps_gen = sdhci_readl(host, caps_ptr + SDHCI_UHS2_CAPS_OFFSET); in sdhci_uhs2_init()
373 caps_phy = sdhci_readl(host, caps_ptr + SDHCI_UHS2_CAPS_PHY_OFFSET); in sdhci_uhs2_init()
701 if (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) in sdhci_uhs2_send_command()
807 sdhci_readl(host, SDHCI_UHS2_RESPONSE); in __sdhci_uhs2_finish_command()
1054 uhs2mask = sdhci_readl(host, SDHCI_UHS2_INT_STATUS); in sdhci_uhs2_irq()
[all …]
H A Dsdhci-pci-gli.c295 wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT); in gl9750_wt_on()
312 wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT); in gl9750_wt_off()
337 pll_value = sdhci_readl(host, SDHCI_GLI_9750_PLL); in gli_set_9750()
496 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL); in gl9750_disable_ssc_pll()
507 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL); in gl9750_set_pll()
527 misc = sdhci_readl(host, SDHCI_GLI_9750_MISC); in gl9750_ssc_enable()
540 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL); in gl9750_set_ssc()
541 ssc = sdhci_readl(host, SDHCI_GLI_9750_PLLSSC); in gl9750_set_ssc()
617 value = sdhci_readl(host, SDHCI_GLI_9750_CFG2); in gl9750_hw_setting()
922 mask = sdhci_readl(host, SDHCI_SIGNAL_ENABLE); in sdhci_gli_overcurrent_event_enable()
[all …]
H A Dsdhci-sprd.c123 val = sdhci_readl(host, SDHCI_SPRD_REG_DEBOUNCE); in sdhci_sprd_init_config()
197 dll_dly_offset = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); in sdhci_sprd_set_dll_invert()
241 val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI); in _sdhci_sprd_set_clock()
261 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); in sdhci_sprd_enable_phy_dll()
267 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); in sdhci_sprd_enable_phy_dll()
274 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); in sdhci_sprd_enable_phy_dll()
280 if (read_poll_timeout(sdhci_readl, tmp, (tmp & SDHCI_SPRD_DLL_LOCKED), in sdhci_sprd_enable_phy_dll()
285 sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_STS0), in sdhci_sprd_enable_phy_dll()
286 sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG)); in sdhci_sprd_enable_phy_dll()
645 dll_cfg = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); in sdhci_sprd_tuning()
H A Dsdhci-tegra.c352 reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); in tegra_sdhci_set_tap()
430 val = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); in tegra_sdhci_configure_cal_pad()
448 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); in tegra_sdhci_set_pad_autocal_offset()
493 reg = sdhci_readl(host, in tegra_sdhci_set_padctrl()
557 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); in tegra_sdhci_pad_autocalib()
575 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); in tegra_sdhci_pad_autocalib()
840 reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_DLLCAL_CFG); in tegra_sdhci_hs400_dll_cal()
877 val = sdhci_readl(host, SDHCI_VNDR_TUN_CTRL0_0); in tegra_sdhci_tap_correction()
948 val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); in tegra_sdhci_post_tuning()
1041 val = sdhci_readl(host, SDHCI_VNDR_TUN_CTRL0_0); in tegra_sdhci_set_uhs_signaling()
[all …]
H A Dsdhci.c57 sdhci_readl(host, SDHCI_DMA_ADDRESS), in sdhci_dumpregs()
63 sdhci_readl(host, SDHCI_ARGUMENT), in sdhci_dumpregs()
66 sdhci_readl(host, SDHCI_PRESENT_STATE), in sdhci_dumpregs()
76 sdhci_readl(host, SDHCI_INT_STATUS)); in sdhci_dumpregs()
78 sdhci_readl(host, SDHCI_INT_ENABLE), in sdhci_dumpregs()
84 sdhci_readl(host, SDHCI_CAPABILITIES), in sdhci_dumpregs()
88 sdhci_readl(host, SDHCI_MAX_CURRENT)); in sdhci_dumpregs()
90 sdhci_readl(host, SDHCI_RESPONSE), in sdhci_dumpregs()
93 sdhci_readl(host, SDHCI_RESPONSE + 8), in sdhci_dumpregs()
101 sdhci_readl(host, SDHCI_ADMA_ERROR), in sdhci_dumpregs()
[all …]
H A Dsdhci-of-dwcmshc.c471 vendor = sdhci_readl(host, reg); in dwcmshc_hs400_enhanced_strobe()
593 extra = sdhci_readl(host, reg); in dwcmshc_rk3568_set_clock()
783 val = sdhci_readl(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); in th1520_execute_tuning()
811 val = sdhci_readl(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); in th1520_execute_tuning()
897 val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL); in cv18xx_sdhci_reset()
923 val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL); in cv18xx_sdhci_set_tap()
957 val = sdhci_readl(host, SDHCI_INT_STATUS); in cv18xx_sdhci_post_tuning()
1024 val = sdhci_readl(host, PHY_CNFG_R); in sg2042_sdhci_phy_init()
1076 val = sdhci_readl(host, PHY_CNFG_R); in sg2042_sdhci_phy_init()
1411 sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK; in dwcmshc_probe()
[all …]
H A Dsdhci-pci-o2micro.c94 scratch32 = sdhci_readl(host, SDHCI_PRESENT_STATE); in sdhci_o2_wait_card_detect_stable()
116 scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_enable_internal_clock()
150 scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_enable_internal_clock()
164 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); in sdhci_o2_get_cd()
183 return sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_pll_dll_wdt_control()
263 scratch_32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_dll_recovery()
737 caps = sdhci_readl(host, SDHCI_CAPABILITIES); in sdhci_pci_o2_probe_slot()
757 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING); in sdhci_pci_o2_probe_slot()
789 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING2); in sdhci_pci_o2_probe_slot()
H A Dsdhci-brcmstb.c72 reg = sdhci_readl(host, SDHCI_VENDOR); in enable_clock_gating()
97 reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL); in brcmstb_sdhci_reset_cmd_data()
225 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); in sdhci_brcmstb_cqe_enable()
227 sdhci_readl(host, SDHCI_BUFFER); in sdhci_brcmstb_cqe_enable()
228 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); in sdhci_brcmstb_cqe_enable()
H A Dsdhci-of-arasan.c456 vendor = sdhci_readl(host, SDHCI_ARASAN_VENDOR_REGISTER); in sdhci_arasan_hs400_enhanced_strobe()
551 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); in sdhci_arasan_cqe_enable()
553 sdhci_readl(host, SDHCI_BUFFER); in sdhci_arasan_cqe_enable()
554 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); in sdhci_arasan_cqe_enable()
920 regval = sdhci_readl(host, SDHCI_ARASAN_OTAPDLY_REGISTER); in sdhci_versal_sdcardclk_set_phase()
987 regval = sdhci_readl(host, SDHCI_ARASAN_ITAPDLY_REGISTER); in sdhci_versal_sampleclk_set_phase()
1036 regval = sdhci_readl(host, PHY_CTRL_REG1); in sdhci_versal_net_emmc_sdcardclk_set_phase()
1069 regval = sdhci_readl(host, PHY_CTRL_REG1); in sdhci_versal_net_emmc_sampleclk_set_phase()
1082 regval = sdhci_readl(host, PHY_CTRL_REG1); in sdhci_versal_net_emmc_sampleclk_set_phase()
H A Dsdhci-of-sparx5.c233 mmc_hostname(host->mmc), sdhci_readl(host, MSHC2_VERSION)); in sdhci_sparx5_probe()
235 mmc_hostname(host->mmc), sdhci_readl(host, MSHC2_TYPE)); in sdhci_sparx5_probe()
H A Dsdhci-npcm.c55 caps = sdhci_readl(host, SDHCI_CAPABILITIES); in npcm_sdhci_probe()
H A Dsdhci-of-at91.c126 u32 calcr = sdhci_readl(host, SDMMC_CALCR); in sdhci_at91_reset()
131 if (read_poll_timeout(sdhci_readl, tmp, !(tmp & SDMMC_CALCR_EN), in sdhci_at91_reset()
H A Dsdhci-acpi.c318 sdhci_readl(host, SDHCI_CAPABILITIES) == 0x446cc8b2 && in intel_probe_slot()
319 sdhci_readl(host, SDHCI_CAPABILITIES_1) == 0x00000807) in intel_probe_slot()
970 dead = (sdhci_readl(c->host, SDHCI_INT_STATUS) == ~0); in sdhci_acpi_remove()
H A Dsdhci-esdhc-imx.c969 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); in esdhc_pltfm_set_clock()
997 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); in esdhc_pltfm_set_clock()
1584 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); in esdhc_cqe_enable()
1586 sdhci_readl(host, SDHCI_BUFFER); in esdhc_cqe_enable()
1587 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); in esdhc_cqe_enable()
H A Dsdhci.h755 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) in sdhci_readl() function
796 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) in sdhci_readl() function
H A Dsdhci-of-ma35d1.c153 regs[idx] = sdhci_readl(host, restore_data[idx].reg); in ma35_execute_tuning()
H A Dsdhci-pci-core.c652 val = sdhci_readl(host, INTEL_HS400_ES_REG); in intel_hs400_enhanced_strobe()
1011 glk_rx_ctrl1 = sdhci_readl(host, GLK_RX_CTRL1); in glk_rpm_retune_wa()
1012 glk_tun_val = sdhci_readl(host, GLK_TUN_VAL); in glk_rpm_retune_wa()
1808 return sdhci_readl(host, SDHCI_PRESENT_STATE); in sdhci_read_present_state()
H A Dsdhci-of-aspeed.c102 cap_val = sdhci_readl(host, 0x40 + (cap_reg * 4)); in aspeed_sdc_set_slot_capability()

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