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Searched refs:rtw89_write32_mask (Results 1 – 22 of 22) sorted by relevance

/linux-6.15/drivers/net/wireless/realtek/rtw89/
H A Dphy_be.c327 rtw89_write32_mask(rtwdev, addr, B_BE_PWR_OFST_LMT_DB, 0); in rtw89_phy_bb_wrap_tpu_set_all()
329 rtw89_write32_mask(rtwdev, addr, B_BE_PWR_OFST_LMTBF_DB, 0); in rtw89_phy_bb_wrap_tpu_set_all()
331 rtw89_write32_mask(rtwdev, addr, B_BE_PWR_OFST_BYRATE_DB, 0); in rtw89_phy_bb_wrap_tpu_set_all()
333 rtw89_write32_mask(rtwdev, addr, B_BE_PWR_OFST_RULMT_DB, 0); in rtw89_phy_bb_wrap_tpu_set_all()
335 rtw89_write32_mask(rtwdev, addr, B_BE_PWR_OFST_SW_DB, 0); in rtw89_phy_bb_wrap_tpu_set_all()
358 rtw89_write32_mask(rtwdev, addr, B_BE_PWR_FORCE_LMT_ON, 0); in rtw89_phy_bb_wrap_force_cr_init()
360 rtw89_write32_mask(rtwdev, addr, B_BE_PWR_FORCE_RATE_ON, 0); in rtw89_phy_bb_wrap_force_cr_init()
362 rtw89_write32_mask(rtwdev, addr, B_BE_PWR_FORCE_RU_ENON, 0); in rtw89_phy_bb_wrap_force_cr_init()
363 rtw89_write32_mask(rtwdev, addr, B_BE_PWR_FORCE_RU_ON, 0); in rtw89_phy_bb_wrap_force_cr_init()
367 rtw89_write32_mask(rtwdev, addr, B_BE_PWR_FORCE_COEX_ON, 0); in rtw89_phy_bb_wrap_force_cr_init()
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H A Dmac_be.c852 rtw89_write32_mask(rtwdev, reg, B_BE_PREBKF_TIME_MASK, in scheduler_init_be()
856 rtw89_write32_mask(rtwdev, reg, B_BE_PREBKF_TIME_NONAC_MASK, in scheduler_init_be()
861 rtw89_write32_mask(rtwdev, reg, B_BE_BCNQ_CW_MASK, 0x32); in scheduler_init_be()
862 rtw89_write32_mask(rtwdev, reg, B_BE_BCNQ_AIFS_MASK, BCN_IFS_25US); in scheduler_init_be()
1074 rtw89_write32_mask(rtwdev, reg, B_BE_RSC_MASK, 1); in trxptcl_init_be()
1085 rtw89_write32_mask(rtwdev, R_BE_RESPBA_CAM_CTRL, B_BE_BACAM_RST_MASK, in rst_bacam_be()
1466 rtw89_write32_mask(rtwdev, R_BE_WDE_BUFMGN_CTL, in dle_upd_qta_aval_page_be()
1474 rtw89_write32_mask(rtwdev, R_BE_PLE_BUFMGN_CTL, in dle_upd_qta_aval_page_be()
1997 rtw89_write32_mask(rtwdev, reg, B_BE_PHY_RPT_SZ_MASK, val); in rtw89_mac_cfg_phy_rpt_be()
2001 rtw89_write32_mask(rtwdev, reg, B_BE_DRV_INFO_PHYRPT_EN, enable); in rtw89_mac_cfg_phy_rpt_be()
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H A Dmac.c389 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, in rtw89_mac_dump_dmac_err_status()
391 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, in rtw89_mac_dump_dmac_err_status()
393 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, in rtw89_mac_dump_dmac_err_status()
396 rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL, in rtw89_mac_dump_dmac_err_status()
1119 rtw89_write32_mask(rtwdev, regs->hci_fc_ctrl, in hfc_h2c_cfg_ax()
2304 rtw89_write32_mask(rtwdev, R_AX_SEC_DEBUG1, in sec_eng_init_ax()
2806 rtw89_write32_mask(rtwdev, reg, in ptcl_init_ax()
3745 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, in set_host_rpr_ax()
3750 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, in set_host_rpr_ax()
3900 rtw89_write32_mask(rtwdev, R_AX_SEC_CTRL, in rtw89_mac_enable_cpu_ax()
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H A Drtw8852b.c286 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_OFF_CTRL0, B_AX_C1_L1_MASK, 0x1); in rtw8852b_pwr_on_func()
287 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_OFF_CTRL0, B_AX_C3_L1_MASK, 0x3); in rtw8852b_pwr_on_func()
361 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_VOL_L1_MASK, 0x9); in rtw8852b_pwr_on_func()
362 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_VREFPFM_L_MASK, 0xA); in rtw8852b_pwr_on_func()
384 rtw89_write32_mask(rtwdev, R_AX_EECS_EESK_FUNC_SEL, B_AX_PINMUX_EESK_FUNC_SEL_MASK, in rtw8852b_pwr_on_func()
448 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_REG_ZCDC_H_MASK, 0x3); in rtw8852b_pwr_off_func()
H A Dpci_be.c59 rtw89_write32_mask(rtwdev, R_BE_PCIE_LAT_CTRL, B_BE_CLK_REQ_LAT_MASK, in rtw89_pci_clkreq_set_be()
158 rtw89_write32_mask(rtwdev, R_BE_HAXI_MST_WDT_TIMEOUT_SEL_V1, in rtw89_pci_ctrl_trxdma_pcie_be()
312 rtw89_write32_mask(rtwdev, R_BE_SER_PL1_CTRL, B_BE_PL1_TIMER_UNIT_MASK, 1); in rtw89_pci_ser_setting_be()
471 rtw89_write32_mask(rtwdev, R_BE_PCIE_MIT0_TMR, in rtw89_pci_configure_mit_be()
H A Drtw8852bt.c263 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_OCP_L1_MASK, 7); in rtw8852bt_pwr_on_func()
341 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_VOL_L1_MASK, 0x9); in rtw8852bt_pwr_on_func()
342 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_VREFPFM_L_MASK, 0xA); in rtw8852bt_pwr_on_func()
358 rtw89_write32_mask(rtwdev, R_AX_EECS_EESK_FUNC_SEL, in rtw8852bt_pwr_on_func()
420 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_REG_ZCDC_H_MASK, 0x3); in rtw8852bt_pwr_off_func()
H A Dpci.c2778 rtw89_write32_mask(rtwdev, R_AX_PCIE_INIT_CFG2, in rtw89_pci_mode_op()
2802 rtw89_write32_mask(rtwdev, info->exp_ctrl_reg, info->max_tag_num_mask, in rtw89_pci_mode_op()
2806 rtw89_write32_mask(rtwdev, R_AX_PCIE_INIT_CFG2, B_AX_WD_ITVL_IDLE, in rtw89_pci_mode_op()
2808 rtw89_write32_mask(rtwdev, R_AX_PCIE_INIT_CFG2, B_AX_WD_ITVL_ACT, in rtw89_pci_mode_op()
2952 rtw89_write32_mask(rtwdev, R_AX_LTR_CTRL_0, B_AX_LTR_SPACE_IDX_MASK, in rtw89_pci_ltr_set()
2954 rtw89_write32_mask(rtwdev, R_AX_LTR_CTRL_0, B_AX_LTR_IDLE_TIMER_IDX_MASK, in rtw89_pci_ltr_set()
2956 rtw89_write32_mask(rtwdev, R_AX_LTR_CTRL_1, B_AX_LTR_RX0_TH_MASK, 0x28); in rtw89_pci_ltr_set()
2957 rtw89_write32_mask(rtwdev, R_AX_LTR_CTRL_1, B_AX_LTR_RX1_TH_MASK, 0x28); in rtw89_pci_ltr_set()
3000 rtw89_write32_mask(rtwdev, R_AX_LTR_CTRL_0, B_AX_LTR_IDLE_TIMER_IDX_MASK, in rtw89_pci_ltr_set_v1()
3002 rtw89_write32_mask(rtwdev, R_AX_LTR_CTRL_1, B_AX_LTR_RX0_TH_MASK, 0x28); in rtw89_pci_ltr_set_v1()
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H A Drtw8922a.c871 rtw89_write32_mask(rtwdev, reg, B_BE_SIFS_MACTXEN_T1_MASK, 0x41); in rtw8922a_set_channel_mac()
873 rtw89_write32_mask(rtwdev, reg, B_BE_SIFS_MACTXEN_TB_T1_MASK, 0x41); in rtw8922a_set_channel_mac()
877 rtw89_write32_mask(rtwdev, reg, B_BE_SIFS_MACTXEN_T1_MASK, 0x3f); in rtw8922a_set_channel_mac()
879 rtw89_write32_mask(rtwdev, reg, B_BE_SIFS_MACTXEN_TB_T1_MASK, 0x3e); in rtw8922a_set_channel_mac()
1554 rtw89_write32_mask(rtwdev, R_BE_DMAC_SYS_CR32B, dmac_sys_mask[phy_idx], 0x7FF9); in rtw8922a_bb_preinit()
1555 rtw89_write32_mask(rtwdev, R_BE_FEN_RST_ENABLE, glbrst_mask[phy_idx], 0x0); in rtw8922a_bb_preinit()
1556 rtw89_write32_mask(rtwdev, R_BE_FEN_RST_ENABLE, bbrst_mask[phy_idx], 0x0); in rtw8922a_bb_preinit()
1557 rtw89_write32_mask(rtwdev, R_BE_FEN_RST_ENABLE, glbrst_mask[phy_idx], 0x1); in rtw8922a_bb_preinit()
1559 rtw89_write32_mask(rtwdev, R_BE_MEM_PWR_CTRL, B_BE_MEM_BBMCU0_DS_V1, 0); in rtw8922a_bb_preinit()
1871 rtw89_write32_mask(rtwdev, R_BE_PWR_BOOST, B_BE_PWR_CTRL_SEL, 0); in rtw8922a_bb_sethw()
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H A Drtw8852c.c227 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, in rtw8852c_pwr_on_func()
326 rtw89_write32_mask(rtwdev, R_AX_LED1_FUNC_SEL, B_AX_PINMUX_EESK_FUNC_SEL_V1_MASK, in rtw8852c_pwr_on_func()
391 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, in rtw8852c_pwr_off_func()
1736 rtw89_write32_mask(rtwdev, reg, in rtw8852c_set_channel_bb()
1742 rtw89_write32_mask(rtwdev, reg, in rtw8852c_set_channel_bb()
1949 rtw89_write32_mask(rtwdev, reg, in rtw8852c_set_txpwr_ul_tb_offset()
1954 rtw89_write32_mask(rtwdev, reg, in rtw8852c_set_txpwr_ul_tb_offset()
2847 rtw89_write32_mask(rtwdev, R_AX_AFE_OFF_CTRL1, B_AX_S0_LDO_VSEL_F_MASK, 0x1); in rtw8852c_mac_enable_bb_rf()
2848 rtw89_write32_mask(rtwdev, R_AX_AFE_OFF_CTRL1, B_AX_S1_LDO_VSEL_F_MASK, 0x1); in rtw8852c_mac_enable_bb_rf()
H A Defuse.c59 rtw89_write32_mask(rtwdev, R_AX_EFUSE_CTRL_1, B_AX_EF_CELL_SEL_MASK, in rtw89_switch_efuse_bank()
H A Dmac.h1103 rtw89_write32_mask(rtwdev, reg, mask, data); in rtw89_write32_port_mask()
1404 rtw89_write32_mask(rtwdev, cr, mask, val); in rtw89_mac_txpwr_write32_mask()
H A Ddebug.c1449 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, in rtw89_debug_mac_dump_dmac_dbg()
1451 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, in rtw89_debug_mac_dump_dmac_dbg()
1453 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, in rtw89_debug_mac_dump_dmac_dbg()
1456 rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL, in rtw89_debug_mac_dump_dmac_dbg()
2903 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, in rtw89_debug_mac_dbg_port_sel()
2905 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, in rtw89_debug_mac_dbg_port_sel()
3386 rtw89_write32_mask(rtwdev, info->sel_addr, in rtw89_debug_mac_dbg_port_dump()
H A Drtw8852b_common.c1382 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, pw_ofst); in __rtw8852bx_set_txpwr_ul_tb_offset()
1386 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_MASK, pw_ofst); in __rtw8852bx_set_txpwr_ul_tb_offset()
1985 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_REG_ZCDC_H_MASK, 0x1); in __rtw8852bx_mac_enable_bb_rf()
H A Dphy.c4318 rtw89_write32_mask(rtwdev, xtal->xcap_reg, reg_mask, val); in rtw89_phy_cfo_set_xcap_reg()
4410 rtw89_write32_mask(rtwdev, R_AX_PWR_UL_CTRL2, in rtw89_dcfo_comp_init()
4868 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_NORM_BW160, in rtw89_phy_ofdma_power_diff()
4872 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_NORM_BW160, in rtw89_phy_ofdma_power_diff()
4876 rtw89_write32_mask(rtwdev, reg, B_AX_PATH_COM1_NORM_1STS, in rtw89_phy_ofdma_power_diff()
4880 rtw89_write32_mask(rtwdev, reg, B_AX_PATH_COM2_RESP_1STS_PATH, in rtw89_phy_ofdma_power_diff()
6872 rtw89_write32_mask(rtwdev, reg, regs[i].mask, val); in rtw89_phy_tssi_ctrl_set_fast_mode_cfg()
6934 rtw89_write32_mask(rtwdev, reg, regs[i].mask, data[i]); in rtw89_phy_tssi_ctrl_set_bandedge_cfg()
6938 rtw89_write32_mask(rtwdev, reg, B_AX_BANDEDGE_CFG_IDX_MASK, bandedge_cfg); in rtw89_phy_tssi_ctrl_set_bandedge_cfg()
H A Drtw8851b.c394 rtw89_write32_mask(rtwdev, R_AX_EECS_EESK_FUNC_SEL, B_AX_PINMUX_EESK_FUNC_SEL_MASK, in rtw8851b_pwr_on_func()
1799 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, pw_ofst); in rtw8851b_set_txpwr_ul_tb_offset()
1803 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_MASK, pw_ofst); in rtw8851b_set_txpwr_ul_tb_offset()
H A Dmac80211.c354 rtw89_write32_mask(rtwdev, in rtw89_ops_configure_filter()
360 rtw89_write32_mask(rtwdev, in rtw89_ops_configure_filter()
H A Dphy.h590 rtw89_write32_mask(rtwdev, addr + phy->cr_base, mask, data); in rtw89_phy_write32_mask()
H A Drtw8852a.c1441 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, val_1t); in rtw8852a_set_txpwr_ul_tb_offset()
1444 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_MASK, val_2t); in rtw8852a_set_txpwr_ul_tb_offset()
H A Dfw.c1698 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, B_AX_SEL_0XC0_MASK, MAC_DBG_SEL); in rtw89_fw_prog_cnt_dump()
7242 rtw89_write32_mask(rtwdev, reg, B_AX_RX_FLTR_CFG_MASK, rx_fltr); in rtw89_hw_scan_start()
7270 rtw89_write32_mask(rtwdev, reg, B_AX_RX_FLTR_CFG_MASK, rtwdev->hal.rx_fltr); in rtw89_hw_scan_complete_cb()
H A Drtw8851b_rfk.c3137 rtw89_write32_mask(rtwdev, R_AX_PWR_SWING_OTHER_CTRL0, in rtw8851b_by_rate_dpd()
H A Dcore.h6209 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data) in rtw89_write32_mask() function
H A Dcore.c3409 rtw89_write32_mask(rtwdev, reg, B_AX_RX_FLTR_CFG_MASK, rtwdev->hal.rx_fltr); in rtw89_roc_end()