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Searched refs:rtl8xxxu_write32 (Results 1 – 10 of 10) sorted by relevance

/linux-6.15/drivers/net/wireless/realtek/rtl8xxxu/
H A D8192e.c749 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00); in rtl8192eu_rx_iqk_path_a()
770 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); in rtl8192eu_rx_iqk_path_a()
771 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); in rtl8192eu_rx_iqk_path_a()
809 rtl8xxxu_write32(priv, REG_TX_IQK, val32); in rtl8192eu_rx_iqk_path_a()
988 rtl8xxxu_write32(priv, REG_TX_IQK, val32); in rtl8192eu_rx_iqk_path_b()
1344 rtl8xxxu_write32(priv, REG_AFE_CTRL4, val32); in rtl8192e_crystal_afe_adjust()
1359 rtl8xxxu_write32(priv, REG_AFE_CTRL4, val32); in rtl8192e_crystal_afe_adjust()
1417 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); in rtl8192e_emu_to_active()
1649 rtl8xxxu_write32(priv, REG_PWR_DATA, val32); in rtl8192e_enable_rf()
1653 rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32); in rtl8192e_enable_rf()
[all …]
H A D8723b.c543 rtl8xxxu_write32(priv, REG_PAD_CTRL1, val32); in rtl8723bu_phy_init_antenna_selection()
555 rtl8xxxu_write32(priv, REG_LEDCFG0, val32); in rtl8723bu_phy_init_antenna_selection()
559 rtl8xxxu_write32(priv, REG_LEDCFG0, val32); in rtl8723bu_phy_init_antenna_selection()
572 rtl8xxxu_write32(priv, REG_PWR_DATA, val32); in rtl8723bu_phy_init_antenna_selection()
587 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_iqk_path_a()
625 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_iqk_path_a()
660 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_iqk_path_a()
697 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_rx_iqk_path_a()
793 rtl8xxxu_write32(priv, REG_TX_IQK, val32); in rtl8723bu_rx_iqk_path_a()
1452 rtl8xxxu_write32(priv, REG_LEDCFG0, val32); in rtl8723bu_power_on()
[all …]
H A D8192f.c837 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); in rtl8192fu_iqk_path_a()
838 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); in rtl8192fu_iqk_path_a()
918 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); in rtl8192fu_rx_iqk_path_a()
919 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); in rtl8192fu_rx_iqk_path_a()
956 rtl8xxxu_write32(priv, REG_TX_IQK, val32); in rtl8192fu_rx_iqk_path_a()
988 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); in rtl8192fu_rx_iqk_path_a()
1062 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); in rtl8192fu_iqk_path_b()
1063 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); in rtl8192fu_iqk_path_b()
1186 rtl8xxxu_write32(priv, REG_TX_IQK, val32); in rtl8192fu_rx_iqk_path_b()
1216 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); in rtl8192fu_rx_iqk_path_b()
[all …]
H A D8188f.c495 rtl8xxxu_write32(priv, 0xd48, 0x0); in rtl8188f_spur_calibration()
686 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_init_statistics()
843 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_iqk_path_a()
863 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_iqk_path_a()
886 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_iqk_path_a()
916 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_rx_iqk_path_a()
938 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_rx_iqk_path_a()
967 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_rx_iqk_path_a()
985 rtl8xxxu_write32(priv, REG_TX_IQK, val32); in rtl8188fu_rx_iqk_path_a()
992 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_rx_iqk_path_a()
[all …]
H A D8710b.c834 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8710bu_init_statistics()
1005 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8710bu_iqk_path_a()
1028 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8710bu_iqk_path_a()
1053 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8710bu_iqk_path_a()
1089 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8710bu_rx_iqk_path_a()
1112 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8710bu_rx_iqk_path_a()
1165 rtl8xxxu_write32(priv, REG_TX_IQK, val32); in rtl8710bu_rx_iqk_path_a()
1172 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8710bu_rx_iqk_path_a()
1196 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8710bu_rx_iqk_path_a()
1226 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8710bu_rx_iqk_path_a()
[all …]
H A D8188e.c492 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); in rtl8188eu_config_channel()
652 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188eu_rx_iqk_path_a()
663 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188eu_rx_iqk_path_a()
666 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); in rtl8188eu_rx_iqk_path_a()
667 rtl8xxxu_write32(priv, REG_RX_IQK, 0x81004800); in rtl8188eu_rx_iqk_path_a()
699 rtl8xxxu_write32(priv, REG_TX_IQK, val32); in rtl8188eu_rx_iqk_path_a()
704 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188eu_rx_iqk_path_a()
714 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188eu_rx_iqk_path_a()
836 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188eu_phy_iqcalibrate()
876 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188eu_phy_iqcalibrate()
[all …]
H A Dcore.c792 return rtl8xxxu_write32(priv, addr, val32); in rtl8xxxu_write32_set()
801 return rtl8xxxu_write32(priv, addr, val32); in rtl8xxxu_write32_clear()
813 return rtl8xxxu_write32(priv, addr, new); in rtl8xxxu_write32_mask()
1036 rtl8xxxu_write32(priv, mbox_ext_reg, in rtl8xxxu_gen2_h2c_cmd()
2223 ret = rtl8xxxu_write32(priv, reg, val); in rtl8xxxu_init_phy_regs()
3330 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0); in rtl8xxxu_phy_iqcalibrate()
3948 rtl8xxxu_write32(priv, REG_RQPN, val32); in rtl8xxxu_init_queue_reserved_page()
4207 rtl8xxxu_write32(priv, REG_HIMR0, 0x00); in rtl8xxxu_init_device()
4208 rtl8xxxu_write32(priv, REG_HIMR1, 0x00); in rtl8xxxu_init_device()
4237 rtl8xxxu_write32(priv, REG_RCR, val32); in rtl8xxxu_init_device()
[all …]
H A D8723a.c268 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x0381808d); in rtl8723au_init_phy_rf()
269 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83); in rtl8723au_init_phy_rf()
270 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff82); in rtl8723au_init_phy_rf()
271 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83); in rtl8723au_init_phy_rf()
338 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); in rtl8723a_emu_to_active()
409 rtl8xxxu_write32(priv, REG_EFUSE_CTRL, val32); in rtl8723au_power_on()
438 rtl8xxxu_write32(priv, REG_MAC_PHY_CTRL, val32); in rtl8723a_set_crystal_cap()
H A D8192c.c591 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32); in rtl8192cu_power_on()
H A Drtl8xxxu.h2041 int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val);