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Searched refs:rq_regs (Results 1 – 25 of 51) sorted by relevance

123

/linux-6.15/drivers/gpu/drm/amd/display/dc/hubp/dcn21/
H A Ddcn21_hubp.c141 struct _vcs_dpi_display_rq_regs_st *rq_regs) in hubp21_program_requestor() argument
148 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, in hubp21_program_requestor()
153 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, in hubp21_program_requestor()
159 SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height, in hubp21_program_requestor()
162 CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size, in hubp21_program_requestor()
167 SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height, in hubp21_program_requestor()
175 struct _vcs_dpi_display_rq_regs_st *rq_regs, in hubp21_setup() argument
183 hubp21_program_requestor(hubp, rq_regs); in hubp21_setup()
275 CHUNK_SIZE, &rq_regs.rq_regs_l.chunk_size, in hubp21_validate_dml_output()
281 SWATH_HEIGHT, &rq_regs.rq_regs_l.swath_height, in hubp21_validate_dml_output()
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/linux-6.15/drivers/gpu/drm/amd/display/dc/hubp/dcn201/
H A Ddcn201_hubp.c75 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, in hubp201_program_requestor()
76 PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, in hubp201_program_requestor()
77 MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, in hubp201_program_requestor()
78 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); in hubp201_program_requestor()
82 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, in hubp201_program_requestor()
83 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, in hubp201_program_requestor()
86 SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height); in hubp201_program_requestor()
89 CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size, in hubp201_program_requestor()
93 SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height); in hubp201_program_requestor()
100 struct _vcs_dpi_display_rq_regs_st *rq_regs, in hubp201_setup() argument
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/linux-6.15/drivers/gpu/drm/amd/display/dc/hubp/dcn20/
H A Ddcn20_hubp.c210 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, in hubp2_program_requestor()
216 SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height, in hubp2_program_requestor()
219 CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size, in hubp2_program_requestor()
233 struct _vcs_dpi_display_rq_regs_st *rq_regs, in hubp2_setup() argument
241 hubp2_program_requestor(hubp, rq_regs); in hubp2_setup()
1137 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; in hubp2_read_state_common() local
1327 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; in hubp2_read_state() local
1332 CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size, in hubp2_read_state()
1342 CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size, in hubp2_read_state()
1381 CHUNK_SIZE, &rq_regs.rq_regs_l.chunk_size, in hubp2_validate_dml_output()
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/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/
H A Ddisplay_rq_dlg_helpers.c149 dml_print("DML_RQ_DLG_CALC: chunk_size = 0x%0x\n", rq_regs->chunk_size); in print__data_rq_regs_st()
150 dml_print("DML_RQ_DLG_CALC: min_chunk_size = 0x%0x\n", rq_regs->min_chunk_size); in print__data_rq_regs_st()
154 rq_regs->min_meta_chunk_size); in print__data_rq_regs_st()
157 dml_print("DML_RQ_DLG_CALC: swath_height = 0x%0x\n", rq_regs->swath_height); in print__data_rq_regs_st()
160 rq_regs->pte_row_height_linear); in print__data_rq_regs_st()
169 print__data_rq_regs_st(mode_lib, &rq_regs->rq_regs_l); in print__rq_regs_st()
171 print__data_rq_regs_st(mode_lib, &rq_regs->rq_regs_c); in print__rq_regs_st()
172 dml_print("DML_RQ_DLG_CALC: drq_expansion_mode = 0x%0x\n", rq_regs->drq_expansion_mode); in print__rq_regs_st()
173 dml_print("DML_RQ_DLG_CALC: prq_expansion_mode = 0x%0x\n", rq_regs->prq_expansion_mode); in print__rq_regs_st()
174 dml_print("DML_RQ_DLG_CALC: mrq_expansion_mode = 0x%0x\n", rq_regs->mrq_expansion_mode); in print__rq_regs_st()
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H A Ddisplay_rq_dlg_helpers.h40 …regs_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_data_rq_regs_st *rq_regs);
41 …__rq_regs_st(struct display_mode_lib *mode_lib, const struct _vcs_dpi_display_rq_regs_st *rq_regs);
H A Ddml1_display_rq_dlg_calc.c208 struct _vcs_dpi_display_data_rq_regs_st *rq_regs, in extract_rq_sizing_regs() argument
214 rq_regs->chunk_size = dml_log2(rq_sizing->chunk_bytes) - 10; in extract_rq_sizing_regs()
217 rq_regs->min_chunk_size = 0; in extract_rq_sizing_regs()
223 rq_regs->min_meta_chunk_size = 0; in extract_rq_sizing_regs()
233 struct _vcs_dpi_display_rq_regs_st *rq_regs, in dml1_extract_rq_regs() argument
250 rq_regs->drq_expansion_mode = 0; in dml1_extract_rq_regs()
252 rq_regs->drq_expansion_mode = 2; in dml1_extract_rq_regs()
254 rq_regs->prq_expansion_mode = 1; in dml1_extract_rq_regs()
255 rq_regs->mrq_expansion_mode = 1; in dml1_extract_rq_regs()
256 rq_regs->crq_expansion_mode = 1; in dml1_extract_rq_regs()
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H A Ddisplay_mode_lib.h65 display_rq_regs_st *rq_regs,
76 void (*rq_dlg_get_rq_reg_v2)(display_rq_regs_st *rq_regs,
/linux-6.15/drivers/gpu/drm/amd/display/dc/hubp/dcn10/
H A Ddcn10_hubp.c574 struct _vcs_dpi_display_rq_regs_st *rq_regs) in hubp1_program_requestor() argument
586 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, in hubp1_program_requestor()
592 SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height, in hubp1_program_requestor()
595 CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size, in hubp1_program_requestor()
601 SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height, in hubp1_program_requestor()
698 struct _vcs_dpi_display_rq_regs_st *rq_regs, in hubp1_setup() argument
704 hubp1_program_requestor(hubp, rq_regs); in hubp1_setup()
894 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; in hubp1_read_state_common() local
1096 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; in hubp1_read_state() local
1101 CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size, in hubp1_read_state()
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/linux-6.15/drivers/gpu/drm/amd/display/dc/dml2/
H A Ddml_display_rq_dlg_calc.c73 memset(rq_regs, 0, sizeof(*rq_regs)); in dml_rq_dlg_get_rq_reg()
101 rq_regs->rq_regs_l.min_chunk_size = 0; in dml_rq_dlg_get_rq_reg()
106 rq_regs->rq_regs_c.min_chunk_size = 0; in dml_rq_dlg_get_rq_reg()
114 rq_regs->rq_regs_l.min_meta_chunk_size = 0; in dml_rq_dlg_get_rq_reg()
119 rq_regs->rq_regs_c.min_meta_chunk_size = 0; in dml_rq_dlg_get_rq_reg()
149 rq_regs->drq_expansion_mode = 0; in dml_rq_dlg_get_rq_reg()
151 rq_regs->drq_expansion_mode = 2; in dml_rq_dlg_get_rq_reg()
153 rq_regs->prq_expansion_mode = 1; in dml_rq_dlg_get_rq_reg()
154 rq_regs->mrq_expansion_mode = 1; in dml_rq_dlg_get_rq_reg()
155 rq_regs->crq_expansion_mode = 1; in dml_rq_dlg_get_rq_reg()
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H A Ddml2_translation_helper.c1449 memset(&out->rq_regs, 0, sizeof(out->rq_regs)); in dml2_update_pipe_ctx_dchub_regs()
1450 out->rq_regs.rq_regs_l.chunk_size = rq_regs->rq_regs_l.chunk_size; in dml2_update_pipe_ctx_dchub_regs()
1451 out->rq_regs.rq_regs_l.min_chunk_size = rq_regs->rq_regs_l.min_chunk_size; in dml2_update_pipe_ctx_dchub_regs()
1456 out->rq_regs.rq_regs_l.swath_height = rq_regs->rq_regs_l.swath_height; in dml2_update_pipe_ctx_dchub_regs()
1459 out->rq_regs.rq_regs_c.chunk_size = rq_regs->rq_regs_c.chunk_size; in dml2_update_pipe_ctx_dchub_regs()
1465 out->rq_regs.rq_regs_c.swath_height = rq_regs->rq_regs_c.swath_height; in dml2_update_pipe_ctx_dchub_regs()
1468 out->rq_regs.drq_expansion_mode = rq_regs->drq_expansion_mode; in dml2_update_pipe_ctx_dchub_regs()
1469 out->rq_regs.prq_expansion_mode = rq_regs->prq_expansion_mode; in dml2_update_pipe_ctx_dchub_regs()
1470 out->rq_regs.mrq_expansion_mode = rq_regs->mrq_expansion_mode; in dml2_update_pipe_ctx_dchub_regs()
1471 out->rq_regs.crq_expansion_mode = rq_regs->crq_expansion_mode; in dml2_update_pipe_ctx_dchub_regs()
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H A Ddisplay_mode_util.c218 void dml_print_data_rq_regs_st(const dml_display_plane_rq_regs_st *rq_regs) in dml_print_data_rq_regs_st() argument
222 dml_print("DML: chunk_size = 0x%x\n", rq_regs->chunk_size); in dml_print_data_rq_regs_st()
223 dml_print("DML: min_chunk_size = 0x%x\n", rq_regs->min_chunk_size); in dml_print_data_rq_regs_st()
224 dml_print("DML: meta_chunk_size = 0x%x\n", rq_regs->meta_chunk_size); in dml_print_data_rq_regs_st()
226 dml_print("DML: dpte_group_size = 0x%x\n", rq_regs->dpte_group_size); in dml_print_data_rq_regs_st()
227 dml_print("DML: mpte_group_size = 0x%x\n", rq_regs->mpte_group_size); in dml_print_data_rq_regs_st()
228 dml_print("DML: swath_height = 0x%x\n", rq_regs->swath_height); in dml_print_data_rq_regs_st()
233 void dml_print_rq_regs_st(const dml_display_rq_regs_st *rq_regs) in dml_print_rq_regs_st() argument
238 dml_print_data_rq_regs_st(&rq_regs->rq_regs_l); in dml_print_rq_regs_st()
240 dml_print_data_rq_regs_st(&rq_regs->rq_regs_c); in dml_print_rq_regs_st()
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H A Ddml_display_rq_dlg_calc.h43 void dml_rq_dlg_get_rq_reg(dml_display_rq_regs_st *rq_regs,
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddisplay_rq_dlg_calc_32.c72 memset(rq_regs, 0, sizeof(*rq_regs)); in dml32_rq_dlg_get_rq_reg()
102 rq_regs->rq_regs_l.min_chunk_size = 0; in dml32_rq_dlg_get_rq_reg()
107 rq_regs->rq_regs_c.min_chunk_size = 0; in dml32_rq_dlg_get_rq_reg()
115 rq_regs->rq_regs_l.min_meta_chunk_size = 0; in dml32_rq_dlg_get_rq_reg()
120 rq_regs->rq_regs_c.min_meta_chunk_size = 0; in dml32_rq_dlg_get_rq_reg()
155 rq_regs->drq_expansion_mode = 0; in dml32_rq_dlg_get_rq_reg()
157 rq_regs->drq_expansion_mode = 2; in dml32_rq_dlg_get_rq_reg()
159 rq_regs->prq_expansion_mode = 1; in dml32_rq_dlg_get_rq_reg()
160 rq_regs->mrq_expansion_mode = 1; in dml32_rq_dlg_get_rq_reg()
161 rq_regs->crq_expansion_mode = 1; in dml32_rq_dlg_get_rq_reg()
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H A Ddisplay_rq_dlg_calc_32.h44 void dml32_rq_dlg_get_rq_reg(display_rq_regs_st *rq_regs,
/linux-6.15/drivers/gpu/drm/amd/display/dc/hubp/dcn401/
H A Ddcn401_hubp.c185 struct dml2_display_rq_regs *rq_regs) in hubp401_program_requestor() argument
192 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, in hubp401_program_requestor()
193 PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, in hubp401_program_requestor()
194 MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, in hubp401_program_requestor()
197 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, in hubp401_program_requestor()
201 SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height, in hubp401_program_requestor()
204 CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size, in hubp401_program_requestor()
207 SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height, in hubp401_program_requestor()
791 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; in hubp401_read_state() local
803 CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size, in hubp401_read_state()
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/linux-6.15/drivers/gpu/drm/amd/display/dc/hubp/dcn30/
H A Ddcn30_hubp.c446 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; in hubp3_read_state() local
451 CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size, in hubp3_read_state()
452 MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size, in hubp3_read_state()
453 META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size, in hubp3_read_state()
455 DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size, in hubp3_read_state()
456 SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height, in hubp3_read_state()
460 CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size, in hubp3_read_state()
461 MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size, in hubp3_read_state()
465 SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height, in hubp3_read_state()
483 struct _vcs_dpi_display_rq_regs_st *rq_regs, in hubp3_setup() argument
[all …]
/linux-6.15/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_hw_sequencer_debug.c206 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs; in dcn10_get_rq_states() local
213 …pool->hubps[i]->inst, rq_regs->drq_expansion_mode, rq_regs->prq_expansion_mode, rq_regs->mrq_expan… in dcn10_get_rq_states()
214 rq_regs->crq_expansion_mode, rq_regs->plane1_base_address, rq_regs->rq_regs_l.chunk_size, in dcn10_get_rq_states()
215 rq_regs->rq_regs_l.min_chunk_size, rq_regs->rq_regs_l.meta_chunk_size, in dcn10_get_rq_states()
216 rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs->rq_regs_l.dpte_group_size, in dcn10_get_rq_states()
217 rq_regs->rq_regs_l.mpte_group_size, rq_regs->rq_regs_l.swath_height, in dcn10_get_rq_states()
218 …rq_regs->rq_regs_l.pte_row_height_linear, rq_regs->rq_regs_c.chunk_size, rq_regs->rq_regs_c.min_ch… in dcn10_get_rq_states()
219 rq_regs->rq_regs_c.meta_chunk_size, rq_regs->rq_regs_c.min_meta_chunk_size, in dcn10_get_rq_states()
220 rq_regs->rq_regs_c.dpte_group_size, rq_regs->rq_regs_c.mpte_group_size, in dcn10_get_rq_states()
221 rq_regs->rq_regs_c.swath_height, rq_regs->rq_regs_c.pte_row_height_linear); in dcn10_get_rq_states()
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn21/
H A Ddisplay_rq_dlg_calc_21.c143 display_data_rq_regs_st *rq_regs, in extract_rq_sizing_regs() argument
152 rq_regs->min_chunk_size = 0; in extract_rq_sizing_regs()
158 rq_regs->min_meta_chunk_size = 0; in extract_rq_sizing_regs()
168 display_rq_regs_st *rq_regs, in extract_rq_regs() argument
193 rq_regs->drq_expansion_mode = 0; in extract_rq_regs()
195 rq_regs->drq_expansion_mode = 2; in extract_rq_regs()
197 rq_regs->prq_expansion_mode = 1; in extract_rq_regs()
198 rq_regs->mrq_expansion_mode = 1; in extract_rq_regs()
199 rq_regs->crq_expansion_mode = 1; in extract_rq_regs()
807 display_rq_regs_st *rq_regs, in dml21_rq_dlg_get_rq_reg() argument
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H A Ddisplay_rq_dlg_calc_21.h46 display_rq_regs_st *rq_regs,
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddisplay_rq_dlg_calc_20.c166 display_data_rq_regs_st *rq_regs, in extract_rq_sizing_regs() argument
175 rq_regs->min_chunk_size = 0; in extract_rq_sizing_regs()
181 rq_regs->min_meta_chunk_size = 0; in extract_rq_sizing_regs()
190 display_rq_regs_st *rq_regs, in extract_rq_regs() argument
213 rq_regs->drq_expansion_mode = 0; in extract_rq_regs()
215 rq_regs->drq_expansion_mode = 2; in extract_rq_regs()
217 rq_regs->prq_expansion_mode = 1; in extract_rq_regs()
218 rq_regs->mrq_expansion_mode = 1; in extract_rq_regs()
219 rq_regs->crq_expansion_mode = 1; in extract_rq_regs()
762 display_rq_regs_st *rq_regs, in dml20_rq_dlg_get_rq_reg() argument
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H A Ddisplay_rq_dlg_calc_20v2.c166 display_data_rq_regs_st *rq_regs, in extract_rq_sizing_regs() argument
175 rq_regs->min_chunk_size = 0; in extract_rq_sizing_regs()
181 rq_regs->min_meta_chunk_size = 0; in extract_rq_sizing_regs()
190 display_rq_regs_st *rq_regs, in extract_rq_regs() argument
213 rq_regs->drq_expansion_mode = 0; in extract_rq_regs()
215 rq_regs->drq_expansion_mode = 2; in extract_rq_regs()
217 rq_regs->prq_expansion_mode = 1; in extract_rq_regs()
218 rq_regs->mrq_expansion_mode = 1; in extract_rq_regs()
219 rq_regs->crq_expansion_mode = 1; in extract_rq_regs()
762 display_rq_regs_st *rq_regs, in dml20v2_rq_dlg_get_rq_reg() argument
[all …]
H A Ddisplay_rq_dlg_calc_20.h45 display_rq_regs_st *rq_regs,
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddisplay_rq_dlg_calc_31.c98 rq_regs->min_chunk_size = 0; in extract_rq_sizing_regs()
104 rq_regs->min_meta_chunk_size = 0; in extract_rq_sizing_regs()
132 rq_regs->drq_expansion_mode = 0; in extract_rq_regs()
134 rq_regs->drq_expansion_mode = 2; in extract_rq_regs()
136 rq_regs->prq_expansion_mode = 1; in extract_rq_regs()
137 rq_regs->mrq_expansion_mode = 1; in extract_rq_regs()
138 rq_regs->crq_expansion_mode = 1; in extract_rq_regs()
154 rq_regs->plane1_base_address = detile_buf_plane1_addr; in extract_rq_regs()
768 memset(rq_regs, 0, sizeof(*rq_regs)); in dml31_rq_dlg_get_rq_reg()
770 extract_rq_regs(mode_lib, rq_regs, &rq_param); in dml31_rq_dlg_get_rq_reg()
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/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn30/
H A Ddisplay_rq_dlg_calc_30.c90 display_data_rq_regs_st *rq_regs, in extract_rq_sizing_regs() argument
99 rq_regs->min_chunk_size = 0; in extract_rq_sizing_regs()
105 rq_regs->min_meta_chunk_size = 0; in extract_rq_sizing_regs()
114 display_rq_regs_st *rq_regs, in extract_rq_regs() argument
137 rq_regs->drq_expansion_mode = 0; in extract_rq_regs()
139 rq_regs->drq_expansion_mode = 2; in extract_rq_regs()
141 rq_regs->prq_expansion_mode = 1; in extract_rq_regs()
142 rq_regs->mrq_expansion_mode = 1; in extract_rq_regs()
143 rq_regs->crq_expansion_mode = 1; in extract_rq_regs()
783 display_rq_regs_st *rq_regs, in dml30_rq_dlg_get_rq_reg() argument
[all …]
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn314/
H A Ddisplay_rq_dlg_calc_314.c186 rq_regs->min_chunk_size = 0; in extract_rq_sizing_regs()
192 rq_regs->min_meta_chunk_size = 0; in extract_rq_sizing_regs()
220 rq_regs->drq_expansion_mode = 0; in extract_rq_regs()
222 rq_regs->drq_expansion_mode = 2; in extract_rq_regs()
224 rq_regs->prq_expansion_mode = 1; in extract_rq_regs()
225 rq_regs->mrq_expansion_mode = 1; in extract_rq_regs()
226 rq_regs->crq_expansion_mode = 1; in extract_rq_regs()
242 rq_regs->plane1_base_address = detile_buf_plane1_addr; in extract_rq_regs()
855 memset(rq_regs, 0, sizeof(*rq_regs)); in dml314_rq_dlg_get_rq_reg()
857 extract_rq_regs(mode_lib, rq_regs, &rq_param); in dml314_rq_dlg_get_rq_reg()
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