| /linux-6.15/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_ih.c | 72 ih->rptr_addr = dma_addr + ih->ring_size + 4; in amdgpu_ih_ring_init() 99 ih->rptr_addr = adev->wb.gpu_addr + rptr_offs * 4; in amdgpu_ih_ring_init() 134 amdgpu_device_wb_free(adev, (ih->rptr_addr - ih->gpu_addr) / 4); in amdgpu_ih_ring_fini()
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| H A D | si_dma.c | 131 uint64_t rptr_addr; in si_dma_start() local 151 rptr_addr = ring->rptr_gpu_addr; in si_dma_start() 153 WREG32(DMA_RB_RPTR_ADDR_LO + sdma_offsets[i], lower_32_bits(rptr_addr)); in si_dma_start() 154 WREG32(DMA_RB_RPTR_ADDR_HI + sdma_offsets[i], upper_32_bits(rptr_addr) & 0xFF); in si_dma_start()
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| H A D | amdgpu_ih.h | 65 uint64_t rptr_addr; member
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| H A D | gfx_v6_0.c | 2068 u64 rptr_addr; in gfx_v6_0_cp_gfx_resume() local 2096 rptr_addr = ring->rptr_gpu_addr; in gfx_v6_0_cp_gfx_resume() 2097 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); in gfx_v6_0_cp_gfx_resume() 2098 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); in gfx_v6_0_cp_gfx_resume() 2165 u64 rptr_addr; in gfx_v6_0_cp_compute_resume() local 2182 rptr_addr = ring->rptr_gpu_addr; in gfx_v6_0_cp_compute_resume() 2183 WREG32(mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); in gfx_v6_0_cp_compute_resume() 2184 WREG32(mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); in gfx_v6_0_cp_compute_resume() 2201 rptr_addr = ring->rptr_gpu_addr; in gfx_v6_0_cp_compute_resume() 2202 WREG32(mmCP_RB2_RPTR_ADDR, lower_32_bits(rptr_addr)); in gfx_v6_0_cp_compute_resume() [all …]
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| H A D | gfx_v11_0.c | 3636 u64 rb_addr, rptr_addr, wptr_gpu_addr; in gfx_v11_0_cp_gfx_resume() local 3661 rptr_addr = ring->rptr_gpu_addr; in gfx_v11_0_cp_gfx_resume() 3662 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); in gfx_v11_0_cp_gfx_resume() 3663 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & in gfx_v11_0_cp_gfx_resume() 3699 rptr_addr = ring->rptr_gpu_addr; in gfx_v11_0_cp_gfx_resume() 3700 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); in gfx_v11_0_cp_gfx_resume() 3701 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & in gfx_v11_0_cp_gfx_resume()
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| H A D | gfx_v7_0.c | 2538 u64 rb_addr, rptr_addr; in gfx_v7_0_cp_gfx_resume() local 2569 rptr_addr = ring->rptr_gpu_addr; in gfx_v7_0_cp_gfx_resume() 2570 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); in gfx_v7_0_cp_gfx_resume() 2571 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); in gfx_v7_0_cp_gfx_resume()
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| H A D | gfx_v12_0.c | 2639 u64 rb_addr, rptr_addr, wptr_gpu_addr; in gfx_v12_0_cp_gfx_resume() local 2664 rptr_addr = ring->rptr_gpu_addr; in gfx_v12_0_cp_gfx_resume() 2665 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); in gfx_v12_0_cp_gfx_resume() 2666 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & in gfx_v12_0_cp_gfx_resume()
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| H A D | gfx_v10_0.c | 6466 u64 rb_addr, rptr_addr, wptr_gpu_addr; in gfx_v10_0_cp_gfx_resume() local 6494 rptr_addr = ring->rptr_gpu_addr; in gfx_v10_0_cp_gfx_resume() 6495 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); in gfx_v10_0_cp_gfx_resume() 6496 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & in gfx_v10_0_cp_gfx_resume() 6532 rptr_addr = ring->rptr_gpu_addr; in gfx_v10_0_cp_gfx_resume() 6533 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); in gfx_v10_0_cp_gfx_resume() 6534 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & in gfx_v10_0_cp_gfx_resume()
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| H A D | gfx_v8_0.c | 4254 u64 rb_addr, rptr_addr, wptr_gpu_addr; in gfx_v8_0_cp_gfx_resume() local 4280 rptr_addr = ring->rptr_gpu_addr; in gfx_v8_0_cp_gfx_resume() 4281 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); in gfx_v8_0_cp_gfx_resume() 4282 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); in gfx_v8_0_cp_gfx_resume()
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| H A D | gfx_v9_0.c | 3369 u64 rb_addr, rptr_addr, wptr_gpu_addr; in gfx_v9_0_cp_gfx_resume() local 3393 rptr_addr = ring->rptr_gpu_addr; in gfx_v9_0_cp_gfx_resume() 3394 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); in gfx_v9_0_cp_gfx_resume() 3395 …WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_… in gfx_v9_0_cp_gfx_resume()
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| /linux-6.15/drivers/gpu/drm/msm/adreno/ |
| H A D | a5xx_gpu.h | 115 uint64_t rptr_addr; member
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| H A D | a6xx_gpu.h | 165 u64 rptr_addr; member
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| H A D | a5xx_preempt.c | 235 a5xx_gpu->preempt[i]->rptr_addr = shadowptr(a5xx_gpu, gpu->rb[i]); in a5xx_preempt_hw_init()
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| H A D | a6xx_preempt.c | 202 record_ptr->rptr_addr = shadowptr(a6xx_gpu, gpu->rb[i]); in a6xx_preempt_hw_init()
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