Searched refs:rlc_hdr (Results 1 – 10 of 10) sorted by relevance
354 …adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl… in amdgpu_gfx_rlc_init_microcode_v2_1()358 …adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_o… in amdgpu_gfx_rlc_init_microcode_v2_1()362 …adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_o… in amdgpu_gfx_rlc_init_microcode_v2_1()400 adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes); in amdgpu_gfx_rlc_init_microcode_v2_2()402 adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes); in amdgpu_gfx_rlc_init_microcode_v2_2()432 adev->gfx.rlc.rlcp_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlcp_ucode_offset_bytes); in amdgpu_gfx_rlc_init_microcode_v2_3()437 adev->gfx.rlc.rlcv_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlcv_ucode_offset_bytes); in amdgpu_gfx_rlc_init_microcode_v2_3()467 …adev->gfx.rlc.se0_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se0_tap_delays_ucode_off… in amdgpu_gfx_rlc_init_microcode_v2_4()469 …adev->gfx.rlc.se1_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se1_tap_delays_ucode_off… in amdgpu_gfx_rlc_init_microcode_v2_4()471 …adev->gfx.rlc.se2_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se2_tap_delays_ucode_off… in amdgpu_gfx_rlc_init_microcode_v2_4()[all …]
140 const struct rlc_firmware_header_v1_0 *rlc_hdr = in amdgpu_ucode_print_rlc_hdr() local144 le32_to_cpu(rlc_hdr->ucode_feature_version)); in amdgpu_ucode_print_rlc_hdr()146 le32_to_cpu(rlc_hdr->save_and_restore_offset)); in amdgpu_ucode_print_rlc_hdr()150 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations)); in amdgpu_ucode_print_rlc_hdr()154 const struct rlc_firmware_header_v2_0 *rlc_hdr = in amdgpu_ucode_print_rlc_hdr() local169 le32_to_cpu(rlc_hdr->ucode_feature_version)); in amdgpu_ucode_print_rlc_hdr()173 le32_to_cpu(rlc_hdr->save_and_restore_offset)); in amdgpu_ucode_print_rlc_hdr()179 le32_to_cpu(rlc_hdr->reg_restore_list_size)); in amdgpu_ucode_print_rlc_hdr()181 le32_to_cpu(rlc_hdr->reg_list_format_start)); in amdgpu_ucode_print_rlc_hdr()185 le32_to_cpu(rlc_hdr->starting_offsets_start)); in amdgpu_ucode_print_rlc_hdr()[all …]
946 const struct rlc_firmware_header_v2_0 *rlc_hdr; in gfx_v8_0_init_microcode() local1065 le32_to_cpu(rlc_hdr->save_and_restore_offset); in gfx_v8_0_init_microcode()1069 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations); in gfx_v8_0_init_microcode()1071 le32_to_cpu(rlc_hdr->reg_restore_list_size); in gfx_v8_0_init_microcode()1073 le32_to_cpu(rlc_hdr->reg_list_format_start); in gfx_v8_0_init_microcode()1077 le32_to_cpu(rlc_hdr->starting_offsets_start); in gfx_v8_0_init_microcode()1079 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes); in gfx_v8_0_init_microcode()1081 le32_to_cpu(rlc_hdr->reg_list_size_bytes); in gfx_v8_0_init_microcode()1092 tmp = (unsigned int *)((uintptr_t)rlc_hdr + in gfx_v8_0_init_microcode()1099 tmp = (unsigned int *)((uintptr_t)rlc_hdr + in gfx_v8_0_init_microcode()[all …]
577 const struct rlc_firmware_header_v2_0 *rlc_hdr; in gfx_v12_0_init_microcode() local607 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; in gfx_v12_0_init_microcode()608 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); in gfx_v12_0_init_microcode()609 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); in gfx_v12_0_init_microcode()1100 const struct rlc_firmware_header_v2_0 *rlc_hdr; in gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode() local1162 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) in gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode()1165 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); in gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode()1166 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); in gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode()1170 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); in gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode()1171 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); in gfx_v12_0_rlc_backdoor_autoload_copy_gfx_ucode()
703 const struct rlc_firmware_header_v2_0 *rlc_hdr; in gfx_v11_0_init_microcode() local753 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; in gfx_v11_0_init_microcode()754 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); in gfx_v11_0_init_microcode()755 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); in gfx_v11_0_init_microcode()1310 const struct rlc_firmware_header_v2_0 *rlc_hdr; in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode() local1401 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()1404 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()1405 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()1409 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()1410 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); in gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode()
327 const struct rlc_firmware_header_v1_0 *rlc_hdr; in gfx_v6_0_init_microcode() local382 rlc_hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; in gfx_v6_0_init_microcode()383 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); in gfx_v6_0_init_microcode()384 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); in gfx_v6_0_init_microcode()
533 const struct rlc_firmware_header_v2_0 *rlc_hdr; in gfx_v9_4_3_init_rlc_microcode() local543 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; in gfx_v9_4_3_init_rlc_microcode()545 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); in gfx_v9_4_3_init_rlc_microcode()546 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); in gfx_v9_4_3_init_rlc_microcode()
4182 const struct rlc_firmware_header_v2_0 *rlc_hdr; in gfx_v10_0_init_microcode() local4223 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; in gfx_v10_0_init_microcode()4224 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); in gfx_v10_0_init_microcode()4225 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); in gfx_v10_0_init_microcode()5720 const struct rlc_firmware_header_v2_0 *rlc_hdr; in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode() local5753 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode()5756 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode()5757 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); in gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode()
1466 const struct rlc_firmware_header_v2_0 *rlc_hdr; in gfx_v9_0_init_rlc_microcode() local1500 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; in gfx_v9_0_init_rlc_microcode()1501 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); in gfx_v9_0_init_rlc_microcode()1502 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); in gfx_v9_0_init_rlc_microcode()
115 const struct rlc_firmware_header_v1_0 *rlc_hdr = in radeon_ucode_print_rlc_hdr() local119 le32_to_cpu(rlc_hdr->ucode_feature_version)); in radeon_ucode_print_rlc_hdr()121 le32_to_cpu(rlc_hdr->save_and_restore_offset)); in radeon_ucode_print_rlc_hdr()123 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset)); in radeon_ucode_print_rlc_hdr()125 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations)); in radeon_ucode_print_rlc_hdr()127 le32_to_cpu(rlc_hdr->master_pkt_description_offset)); in radeon_ucode_print_rlc_hdr()