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Searched refs:riscv (Results 1 – 25 of 171) sorted by relevance

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/linux-6.15/arch/riscv/boot/dts/sophgo/
H A Dsg2042-cpus.dtsi259 riscv,isa = "rv64imafdc";
260 riscv,isa-base = "rv64i";
272 mmu-type = "riscv,sv39";
284 riscv,isa = "rv64imafdc";
285 riscv,isa-base = "rv64i";
297 mmu-type = "riscv,sv39";
322 mmu-type = "riscv,sv39";
347 mmu-type = "riscv,sv39";
372 mmu-type = "riscv,sv39";
397 mmu-type = "riscv,sv39";
[all …]
/linux-6.15/arch/riscv/boot/dts/spacemit/
H A Dk1.dtsi55 riscv,isa-base = "rv64i";
71 mmu-type = "riscv,sv39";
85 riscv,isa-base = "rv64i";
101 mmu-type = "riscv,sv39";
115 riscv,isa-base = "rv64i";
131 mmu-type = "riscv,sv39";
145 riscv,isa-base = "rv64i";
161 mmu-type = "riscv,sv39";
191 mmu-type = "riscv,sv39";
221 mmu-type = "riscv,sv39";
[all …]
/linux-6.15/drivers/gpu/drm/tegra/
H A Driscv.c34 writel(value, riscv->regs + offset); in riscv_writel()
37 int tegra_drm_riscv_read_descriptors(struct tegra_drm_riscv *riscv) in tegra_drm_riscv_read_descriptors() argument
39 struct tegra_drm_riscv_descriptor *bl = &riscv->bl_desc; in tegra_drm_riscv_read_descriptors()
40 struct tegra_drm_riscv_descriptor *os = &riscv->os_desc; in tegra_drm_riscv_read_descriptors()
41 const struct device_node *np = riscv->dev->of_node; in tegra_drm_riscv_read_descriptors()
47 dev_err(riscv->dev, "failed to read " name ": %d\n", err); \ in tegra_drm_riscv_read_descriptors()
62 dev_err(riscv->dev, "descriptors not available\n"); in tegra_drm_riscv_read_descriptors()
76 riscv_writel(riscv, RISCV_BCR_CTRL_CORE_SELECT_RISCV, RISCV_BCR_CTRL); in tegra_drm_riscv_boot_bootrom()
91 riscv_writel(riscv, in tegra_drm_riscv_boot_bootrom()
94 riscv_writel(riscv, RISCV_CPUCTL_STARTCPU_TRUE, RISCV_CPUCTL); in tegra_drm_riscv_boot_bootrom()
[all …]
/linux-6.15/Documentation/devicetree/bindings/riscv/
H A Dcpus.yaml66 - const: riscv
72 - const: riscv
86 - riscv,sv32
87 - riscv,sv39
88 - riscv,sv48
89 - riscv,sv57
90 - riscv,none
144 - riscv,isa
146 - riscv,isa-base
149 riscv,isa-base: [ "riscv,isa-extensions" ]
[all …]
H A Dextensions.yaml31 const: riscv
34 riscv,isa:
54 riscv,isa-base:
256 riscv/zawrs") of riscv-isa-manual.
508 riscv-crypto-spec-vector.adoc") of riscv-crypto.
514 riscv-crypto-spec-vector.adoc") of riscv-crypto.
574 riscv-crypto-spec-vector.adoc") of riscv-crypto.
592 riscv-crypto-spec-vector.adoc") of riscv-crypto.
598 riscv-crypto-spec-vector.adoc") of riscv-crypto.
604 riscv-crypto-spec-vector.adoc") of riscv-crypto.
[all …]
/linux-6.15/arch/riscv/
H A DMakefile68 riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima
70 riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd
71 riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c
72 riscv-march-$(CONFIG_RISCV_ISA_V) := $(riscv-march-y)v
82 riscv-march-$(CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI) := $(riscv-march-y)_zicsr_zifencei
86 riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZACAS) := $(riscv-march-y)_zacas
89 riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZABHA) := $(riscv-march-y)_zabha
95 KBUILD_AFLAGS += -march=$(riscv-march-y)
144 boot := arch/riscv/boot
159 boot := arch/riscv/boot
[all …]
/linux-6.15/Documentation/devicetree/bindings/interrupt-controller/
H A Driscv,aplic.yaml16 https://github.com/riscv/riscv-aia.
31 - const: riscv,aplic
57 riscv,num-sources:
65 riscv,children:
78 riscv,delegation:
94 riscv,hart-indexes:
103 riscv,delegation: [ "riscv,children" ]
110 - riscv,num-sources
133 riscv,num-sources = <63>;
145 riscv,num-sources = <63>;
[all …]
H A Driscv,imsics.yaml15 AIA specification can be found at https://github.com/riscv/riscv-aia.
51 - const: riscv,imsics
78 riscv,num-ids:
85 riscv,num-guest-ids:
94 riscv,guest-index-bits:
101 riscv,hart-index-bits:
108 riscv,group-index-bits:
115 riscv,group-index-shift:
131 - riscv,num-ids
150 riscv,num-ids = <127>;
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/linux-6.15/arch/riscv/boot/dts/sifive/
H A Dfu540-c000.dtsi32 riscv,isa = "rv64imac";
33 riscv,isa-base = "rv64i";
56 mmu-type = "riscv,sv39";
58 riscv,isa = "rv64imafdc";
59 riscv,isa-base = "rv64i";
83 mmu-type = "riscv,sv39";
85 riscv,isa = "rv64imafdc";
86 riscv,isa-base = "rv64i";
110 mmu-type = "riscv,sv39";
137 mmu-type = "riscv,sv39";
[all …]
H A Dfu740-c000.dtsi33 riscv,isa = "rv64imac";
34 riscv,isa-base = "rv64i";
57 mmu-type = "riscv,sv39";
60 riscv,isa = "rv64imafdc";
61 riscv,isa-base = "rv64i";
84 mmu-type = "riscv,sv39";
87 riscv,isa = "rv64imafdc";
88 riscv,isa-base = "rv64i";
111 mmu-type = "riscv,sv39";
138 mmu-type = "riscv,sv39";
[all …]
/linux-6.15/arch/riscv/boot/dts/allwinner/
H A Dsun20i-d1s.dtsi15 compatible = "thead,c906", "riscv";
25 mmu-type = "riscv,sv39";
27 riscv,isa = "rv64imafdc";
28 riscv,isa-base = "rv64i";
29 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
35 compatible = "riscv,cpu-intc";
74 riscv,ndev = <175>;
81 compatible = "riscv,pmu";
82 riscv,event-to-mhpmcounters =
93 riscv,event-to-mhpmevent =
[all …]
/linux-6.15/Documentation/devicetree/bindings/iommu/
H A Driscv,iommu.yaml4 $id: http://devicetree.org/schemas/iommu/riscv,iommu.yaml#
22 Visit https://github.com/riscv-non-isa/riscv-iommu for more details.
31 # actually required. For non-PCIe hardware implementations 'riscv,iommu'
37 - qemu,riscv-iommu
38 - const: riscv,iommu
42 - const: riscv,pci-iommu
84 compatible = "qemu,riscv-iommu", "riscv,iommu";
104 compatible = "qemu,riscv-iommu", "riscv,iommu";
114 compatible = "qemu,riscv-iommu", "riscv,iommu";
142 compatible = "pci1efd,edf1", "riscv,pci-iommu";
/linux-6.15/arch/riscv/boot/dts/microchip/
H A Dmpfs.dtsi25 riscv,isa = "rv64imac";
26 riscv,isa-base = "rv64i";
52 mmu-type = "riscv,sv39";
54 riscv,isa = "rv64imafdc";
55 riscv,isa-base = "rv64i";
83 mmu-type = "riscv,sv39";
85 riscv,isa = "rv64imafdc";
86 riscv,isa-base = "rv64i";
114 mmu-type = "riscv,sv39";
145 mmu-type = "riscv,sv39";
[all …]
/linux-6.15/Documentation/devicetree/bindings/perf/
H A Driscv,pmu.yaml4 $id: http://devicetree.org/schemas/perf/riscv,pmu.yaml#
31 https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc
35 const: riscv,pmu
37 riscv,event-to-mhpmevent:
54 riscv,event-to-mhpmcounters:
68 riscv,raw-event-to-mhpmcounters:
93 riscv,event-to-mhpmevent: [ "riscv,event-to-mhpmcounters" ]
103 compatible = "riscv,pmu";
109 riscv,raw-event-to-mhpmcounters =
129 compatible = "riscv,pmu";
[all …]
/linux-6.15/arch/riscv/lib/
H A DMakefile18 obj-$(CONFIG_CRC32_ARCH) += crc32-riscv.o
19 crc32-riscv-y := crc32.o crc32_msb.o crc32_lsb.o
20 obj-$(CONFIG_CRC64_ARCH) += crc64-riscv.o
21 crc64-riscv-y := crc64.o crc64_msb.o crc64_lsb.o
22 obj-$(CONFIG_CRC_T10DIF_ARCH) += crc-t10dif-riscv.o
23 crc-t10dif-riscv-y := crc-t10dif.o crc16_msb.o
/linux-6.15/arch/riscv/kernel/tests/
H A DKconfig.debug2 menu "arch/riscv/kernel Testing and Coverage"
8 bool "arch/riscv/kernel runtime Testing"
11 Enable riscv kernel runtime testing.
16 bool "KUnit test riscv module linking at runtime" if !KUNIT_ALL_TESTS
20 Enable this option to test riscv module linking at boot. This will
35 endmenu # "arch/riscv/kernel runtime Testing"
/linux-6.15/Documentation/arch/riscv/
H A Dacpi.rst9 "riscv-isa-release-1239329-2023-05-23" (commit 1239329
10 ) <https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-isa-release-1239329-2023-05-23>`_
/linux-6.15/arch/riscv/boot/dts/thead/
H A Dth1520.dtsi23 riscv,isa = "rv64imafdc";
24 riscv,isa-base = "rv64i";
35 mmu-type = "riscv,sv39";
47 riscv,isa = "rv64imafdc";
48 riscv,isa-base = "rv64i";
59 mmu-type = "riscv,sv39";
71 riscv,isa = "rv64imafdc";
72 riscv,isa-base = "rv64i";
83 mmu-type = "riscv,sv39";
107 mmu-type = "riscv,sv39";
[all …]
/linux-6.15/arch/riscv/boot/dts/renesas/
H A Dr9a07g043f.dtsi21 compatible = "andestech,ax45mp", "riscv";
26 riscv,isa = "rv64imafdc";
27 riscv,isa-base = "rv64i";
28 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
31 mmu-type = "riscv,sv39";
42 compatible = "andestech,cpu-intc", "riscv,cpu-intc";
136 riscv,ndev = <511>;
/linux-6.15/Documentation/devicetree/bindings/timer/
H A Driscv,timer.yaml4 $id: http://devicetree.org/schemas/timer/riscv,timer.yaml#
20 in Documentation/devicetree/bindings/riscv/cpus.yaml
25 - riscv,timer
31 riscv,timer-cannot-wake-cpu:
46 compatible = "riscv,timer";
/linux-6.15/arch/riscv/boot/dts/starfive/
H A Djh7100.dtsi21 compatible = "sifive,u74-mc", "riscv";
34 mmu-type = "riscv,sv39";
36 riscv,isa = "rv64imafdc";
37 riscv,isa-base = "rv64i";
43 compatible = "riscv,cpu-intc";
50 compatible = "sifive,u74-mc", "riscv";
63 mmu-type = "riscv,sv39";
65 riscv,isa = "rv64imafdc";
66 riscv,isa-base = "rv64i";
72 compatible = "riscv,cpu-intc";
[all …]
H A Djh7110.dtsi30 riscv,isa = "rv64imac_zba_zbb";
31 riscv,isa-base = "rv64i";
57 mmu-type = "riscv,sv39";
60 riscv,isa-base = "rv64i";
90 mmu-type = "riscv,sv39";
93 riscv,isa-base = "rv64i";
123 mmu-type = "riscv,sv39";
126 riscv,isa-base = "rv64i";
156 mmu-type = "riscv,sv39";
159 riscv,isa-base = "rv64i";
[all …]
/linux-6.15/Documentation/devicetree/bindings/cpu/
H A Didle-states.yaml325 http://github.com/riscv/riscv-sbi-doc/riscv-sbi.adoc
370 - riscv,idle-state
381 riscv,sbi-suspend-param:
782 compatible = "riscv";
785 mmu-type = "riscv,sv48";
798 compatible = "riscv";
801 mmu-type = "riscv,sv48";
814 compatible = "riscv";
817 mmu-type = "riscv,sv48";
830 compatible = "riscv";
[all …]
/linux-6.15/arch/riscv/purgatory/
H A DMakefile17 $(obj)/memcpy.o: $(srctree)/arch/riscv/lib/memcpy.S FORCE
20 $(obj)/memset.o: $(srctree)/arch/riscv/lib/memset.S FORCE
23 $(obj)/strcmp.o: $(srctree)/arch/riscv/lib/strcmp.S FORCE
26 $(obj)/strlen.o: $(srctree)/arch/riscv/lib/strlen.S FORCE
29 $(obj)/strncmp.o: $(srctree)/arch/riscv/lib/strncmp.S FORCE
/linux-6.15/arch/riscv/kernel/
H A DMakefile.syscalls3 syscall_abis_32 += riscv memfd_secret
4 syscall_abis_64 += riscv rlimit memfd_secret

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