| /linux-6.15/drivers/bus/fsl-mc/ |
| H A D | fsl-mc-allocator.c | 60 res_pool->free_count > res_pool->max_count) in fsl_mc_resource_pool_add_device()
79 res_pool->free_count++; in fsl_mc_resource_pool_add_device()
80 res_pool->max_count++; in fsl_mc_resource_pool_add_device()
128 res_pool->free_count > res_pool->max_count) { in fsl_mc_resource_pool_remove_device()
146 res_pool->free_count--; in fsl_mc_resource_pool_remove_device()
147 res_pool->max_count--; in fsl_mc_resource_pool_remove_device()
218 res_pool->free_count > res_pool->max_count) in fsl_mc_resource_allocate()
223 res_pool->free_count--; in fsl_mc_resource_allocate()
243 res_pool->free_count >= res_pool->max_count) in fsl_mc_resource_free()
250 res_pool->free_count++; in fsl_mc_resource_free()
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/hwss/dcn31/ |
| H A D | dcn31_hwseq.c | 95 dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode(dc->res_pool->mpc); in enable_memory_low_power()
102 dc->res_pool->stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->stream_enc[i]->vpg); in enable_memory_low_power()
114 struct resource_pool *res_pool = dc->res_pool; in dcn31_init_hw() local
129 res_pool->dccg->funcs->dccg_init(res_pool->dccg); in dcn31_init_hw()
137 if (res_pool->hubbub) { in dcn31_init_hw()
139 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, in dcn31_init_hw()
143 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, in dcn31_init_hw()
215 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, in dcn31_init_hw()
259 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub); in dcn31_init_hw()
272 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); in dcn31_init_hw()
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/hwss/dcn201/ |
| H A D | dcn201_hwseq.c | 228 struct resource_pool *res_pool = dc->res_pool; in dcn201_init_hw() local
231 if (res_pool->dccg->funcs->dccg_init) in dcn201_init_hw()
232 res_pool->dccg->funcs->dccg_init(res_pool->dccg); in dcn201_init_hw()
243 if (res_pool->hubbub) { in dcn201_init_hw()
244 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, in dcn201_init_hw()
248 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, in dcn201_init_hw()
294 res_pool->mpc->funcs->mpc_init(res_pool->mpc); in dcn201_init_hw()
298 res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst; in dcn201_init_hw()
331 res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i]; in dcn201_init_hw()
382 struct mpc *mpc = dc->res_pool->mpc; in dcn201_plane_atomic_disconnect()
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/hwss/dcn35/ |
| H A D | dcn35_hwseq.c | 101 dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode(dc->res_pool->mpc);
135 struct resource_pool *res_pool = dc->res_pool; in dcn35_init_hw() local
152 res_pool->dccg->funcs->dccg_init(res_pool->dccg); in dcn35_init_hw()
162 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, in dcn35_init_hw()
166 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, in dcn35_init_hw()
207 if (res_pool->hubbub && res_pool->hubbub->funcs->dchubbub_init) in dcn35_init_hw()
208 res_pool->hubbub->funcs->dchubbub_init(dc->res_pool->hubbub); in dcn35_init_hw()
289 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub); in dcn35_init_hw()
304 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); in dcn35_init_hw()
1376 dc->res_pool->dccg->funcs->enable_dsc(dc->res_pool->dccg, i); in dcn35_root_clock_control()
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/hwss/dcn30/ |
| H A D | dcn30_hwseq.c | 432 dc->res_pool->mpc->funcs->set_dwb_mux(dc->res_pool->mpc, in dcn30_set_writeback()
481 mcif_wb = dc->res_pool->mcif_wb[0]; in dcn30_mmhubbub_warmup()
558 dc->res_pool->mpc->funcs->disable_dwb_mux(dc->res_pool->mpc, dwb_pipe_inst); in dcn30_disable_writeback()
632 struct resource_pool *res_pool = dc->res_pool; in dcn30_init_hw() local
643 res_pool->dccg->funcs->dccg_init(res_pool->dccg); in dcn30_init_hw()
672 if (res_pool->hubbub) { in dcn30_init_hw()
674 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, in dcn30_init_hw()
678 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, in dcn30_init_hw()
725 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, in dcn30_init_hw()
797 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub); in dcn30_init_hw()
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/hwss/dcn32/ |
| H A D | dcn32_hwseq.c | 781 struct resource_pool *res_pool = dc->res_pool; in dcn32_init_hw() local
792 res_pool->dccg->funcs->dccg_init(res_pool->dccg); in dcn32_init_hw()
814 if (res_pool->hubbub) { in dcn32_init_hw()
815 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, in dcn32_init_hw()
819 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, in dcn32_init_hw()
877 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, in dcn32_init_hw()
964 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub); in dcn32_init_hw()
978 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); in dcn32_init_hw()
1264 hws->ctx->dc->res_pool->dccg->funcs->trigger_dio_fifo_resync(hws->ctx->dc->res_pool->dccg); in dcn32_resync_fifo_dccg_dio()
1656 if (dc->res_pool->opps[i] != NULL && dc->res_pool->opps[i]->inst == opp_id_src0) { in dcn32_init_blank()
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| H A D | dcn401_hwseq.c | 135 struct resource_pool *res_pool = dc->res_pool; in dcn401_init_hw() local
157 res_pool->dccg->funcs->dccg_init(res_pool->dccg); in dcn401_init_hw()
179 if (res_pool->hubbub) { in dcn401_init_hw()
180 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, in dcn401_init_hw()
186 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, in dcn401_init_hw()
244 dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, in dcn401_init_hw()
333 dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub); in dcn401_init_hw()
343 dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); in dcn401_init_hw()
952 dc->res_pool->dccg, in dcn401_enable_stream()
1971 dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes(dc->res_pool->hubbub); in dcn401_program_pipe()
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| H A D | dcn20_hwseq.c | 838 dc->res_pool->dccg, in dcn20_enable_stream_timing()
1942 dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes(dc->res_pool->hubbub); in dcn20_program_pipe()
2349 dc->res_pool->hubbub->funcs->apply_DEDCN21_147_wa(dc->res_pool->hubbub); in dcn20_post_unlock_program_front_end()
2673 dc->res_pool->hubbub->funcs->init_vm_ctx(dc->res_pool->hubbub, &config, vmid); in dcn20_init_vm_ctx()
3049 dc->res_pool->dccg, in dcn20_enable_stream()
3111 struct resource_pool *res_pool = dc->res_pool; in dcn20_fpga_init_hw() local
3119 res_pool->dccg->funcs->dccg_init(res_pool->dccg); in dcn20_fpga_init_hw()
3159 res_pool->mpc->funcs->mpc_init(res_pool->mpc); in dcn20_fpga_init_hw()
3163 res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst; in dcn20_fpga_init_hw()
3198 res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i]; in dcn20_fpga_init_hw()
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/hwss/dcn10/ |
| H A D | dcn10_hwseq.c | 151 dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm); in dcn10_log_hubbub_state()
1463 dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst; in dcn10_init_pipes()
1532 dc->res_pool->dscs[i]->funcs->dsc_read_state(dc->res_pool->dscs[i], &s); in dcn10_init_pipes()
1550 struct resource_pool *res_pool = dc->res_pool; in dcn10_init_hw() local
1565 if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->dccg_init) in dcn10_init_hw()
1566 dc->res_pool->dccg->funcs->dccg_init(res_pool->dccg); in dcn10_init_hw()
1579 if (res_pool->dccg && res_pool->hubbub) { in dcn10_init_hw()
1581 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, in dcn10_init_hw()
1585 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, in dcn10_init_hw()
2044 dc->res_pool->mpc->funcs->cursor_lock(dc->res_pool->mpc, in dcn10_cursor_lock()
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/hwss/dcn351/ |
| H A D | dcn351_hwseq.c | 45 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { in dcn351_calc_blocks_to_gate()
65 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { in dcn351_calc_blocks_to_ungate()
103 struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl; in dcn351_hw_block_power_down()
108 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { in dcn351_hw_block_power_down()
156 struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl; in dcn351_hw_block_power_up()
170 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn351_hw_block_power_up()
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/hwss/dcn314/ |
| H A D | dcn314_hwseq.c | 165 struct mpc *mpc = dc->res_pool->mpc; in dcn314_update_odm()
223 hws->ctx->dc->res_pool->dccg->funcs->enable_dsc && in dcn314_dsc_pg_control()
225 hws->ctx->dc->res_pool->dccg->funcs->enable_dsc( in dcn314_dsc_pg_control()
226 hws->ctx->dc->res_pool->dccg, dsc_inst); in dcn314_dsc_pg_control()
275 hws->ctx->dc->res_pool->dccg->funcs->disable_dsc( in dcn314_dsc_pg_control()
276 hws->ctx->dc->res_pool->dccg, dsc_inst); in dcn314_dsc_pg_control()
390 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn314_resync_fifo_dccg_dio()
411 hws->ctx->dc->res_pool->dccg->funcs->trigger_dio_fifo_resync(hws->ctx->dc->res_pool->dccg); in dcn314_resync_fifo_dccg_dio()
413 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn314_resync_fifo_dccg_dio()
448 hws->ctx->dc->res_pool->dccg, dpp_inst, clock_on); in dcn314_dpp_root_clock_control()
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource_helpers.c | 113 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_merge_pipes_for_subvp()
158 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_all_pipes_have_stream_and_plane()
175 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_subvp_in_use()
200 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_any_surfaces_rotated()
259 for (i = 0; i < dc->res_pool->pipe_count; i++) { in override_det_for_subvp()
274 for (i = 0; i < dc->res_pool->pipe_count; i++) { in override_det_for_subvp()
338 for (j = 0; j < dc->res_pool->pipe_count; j++) { in dcn32_determine_det_override()
349 for (k = 0; k < dc->res_pool->pipe_count; k++) { in dcn32_determine_det_override()
376 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn32_determine_det_override()
655 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_subvp_drr_admissable()
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_link_enc_cfg.c | 41 link_enc = stream->ctx->dc->res_pool->link_encoders[i]; in is_dig_link_enc_stream()
147 stream->link_enc = stream->ctx->dc->res_pool->link_encoders[eng_idx]; in add_link_enc_assignment()
168 for (i = 0; i < ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) { in find_first_avail_link_enc()
177 for (i = 0; i < ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) { in find_first_avail_link_enc()
262 for (i = 0; i < dc->res_pool->res_cap->num_dig_link_enc; i++) { in clear_enc_assignments()
263 if (dc->res_pool->link_encoders[i]) in clear_enc_assignments()
539 for (i = 0; i < dc->res_pool->res_cap->num_dig_link_enc; i++) { in link_enc_cfg_get_next_avail_link_enc()
541 dc->res_pool->link_encoders[i] != NULL) { in link_enc_cfg_get_next_avail_link_enc()
542 link_enc = dc->res_pool->link_encoders[i]; in link_enc_cfg_get_next_avail_link_enc()
559 link->dc->res_pool->funcs->link_encs_assign) { in link_enc_cfg_get_link_enc()
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| H A D | dc.c | 359 if (!dc->res_pool) in destroy_link_encoders()
582 dmcu = dc->res_pool->dmcu; in dc_stream_forward_crc_window()
912 if (dc->res_pool && dc->res_pool->funcs->link_encs_assign && in dc_destruct()
1113 if (!dc->res_pool) in dc_construct()
1121 dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg); in dc_construct()
1383 dc->res_pool->dp_clock_source, in disable_vbios_mode_if_required()
1433 if (dc->res_pool->dmcu != NULL) in dc_create()
1728 dc->res_pool->stream_enc[i]); in dc_validate_boot_timing()
1833 dc->res_pool->dp_clock_source, in dc_validate_boot_timing()
2420 dc->res_pool->dpps[i]->funcs->dpp_deferred_update(dc->res_pool->dpps[i]); in process_deferred_updates()
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| H A D | dc_resource.c | 227 struct resource_pool *res_pool = NULL; in dc_create_resource_pool() local
232 res_pool = dce60_create_resource_pool( in dc_create_resource_pool()
236 res_pool = dce61_create_resource_pool( in dc_create_resource_pool()
337 if (res_pool != NULL) { in dc_create_resource_pool()
355 return res_pool; in dc_create_resource_pool()
361 if (dc->res_pool) in dc_destroy_resource_pool()
362 dc->res_pool->funcs->destroy(&dc->res_pool); in dc_destroy_resource_pool()
4003 if (dc->res_pool == NULL) in dc_resource_is_dsc_encoding_supported()
4373 dc->res_pool, in dc_validate_global_state()
4379 dc->res_pool, in dc_validate_global_state()
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| H A D | dc_surface.c | 73 for (i = 0; i < plane_state->ctx->dc->res_pool->pipe_count; i++) { in dc_plane_get_pipe_mask()
132 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_plane_get_status()
147 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_plane_get_status()
287 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_plane_force_dcc_and_tiling_disable()
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| H A D | dc_link_exports.c | 156 return dc->res_pool->oem_device; in dc_get_oem_i2c_device()
163 if (dc->res_pool->oem_device) in dc_is_oem_i2c_device_present()
165 dc->res_pool, in dc_is_oem_i2c_device_present()
166 dc->res_pool->oem_device, in dc_is_oem_i2c_device_present()
182 dc->res_pool, in dc_submit_i2c()
191 struct ddc_service *ddc = dc->res_pool->oem_device; in dc_submit_i2c_oem()
195 dc->res_pool, in dc_submit_i2c_oem()
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/link/hwss/ |
| H A D | link_hwss_hpo_dp.c | 118 if (link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating) in enable_hpo_dp_link_output()
119 link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating( in enable_hpo_dp_link_output()
120 link->dc->res_pool->dccg, in enable_hpo_dp_link_output()
142 if (link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating) in disable_hpo_dp_link_output()
143 link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating( in disable_hpo_dp_link_output()
144 link->dc->res_pool->dccg, in disable_hpo_dp_link_output()
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/ |
| H A D | dc_edid_parser.c | 35 struct dmcu *dmcu = dc->res_pool->dmcu; in dc_edid_parser_send_cea()
52 struct dmcu *dmcu = dc->res_pool->dmcu; in dc_edid_parser_recv_cea_ack()
68 struct dmcu *dmcu = dc->res_pool->dmcu; in dc_edid_parser_recv_amd_vsdb()
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/hwss/dce110/ |
| H A D | dce110_hwseq.c | 1847 dsc = dc->res_pool->dscs[i]; in clean_up_dsc_blocks()
1857 se = dc->res_pool->stream_enc[i]; in clean_up_dsc_blocks()
1935 dc->res_pool->dccg, in dce110_enable_accelerated_mode()
2195 if (i == dc->res_pool->pipe_count) in should_enable_fbc()
2312 dc->res_pool, in dce110_reset_hw_ctx_wrap()
2363 if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) { in dce110_setup_audio_dto()
2385 if (i == dc->res_pool->pipe_count) { in dce110_setup_audio_dto()
2784 xfm = dc->res_pool->transforms[i]; in init_hw()
2836 abm = dc->res_pool->abm; in init_hw()
2840 dmcu = dc->res_pool->dmcu; in init_hw()
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/dcn10/ |
| H A D | dcn10_hw_sequencer_debug.c | 81 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; in dcn10_get_hubbub_state()
85 dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm); in dcn10_get_hubbub_state()
113 struct resource_pool *pool = dc->res_pool; in dcn10_get_hubp_states()
191 struct resource_pool *pool = dc->res_pool; in dcn10_get_rq_states()
233 struct resource_pool *pool = dc->res_pool; in dcn10_get_dlg_states()
290 struct resource_pool *pool = dc->res_pool; in dcn10_get_ttu_states()
330 struct resource_pool *pool = dc->res_pool; in dcn10_get_cm_states()
385 struct resource_pool *pool = dc->res_pool; in dcn10_get_mpcc_states()
416 struct resource_pool *pool = dc->res_pool; in dcn10_get_otg_states()
493 struct resource_pool *pool = dc->res_pool; in dcn10_clear_otpc_underflow()
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/pg/dcn35/ |
| H A D | dcn35_pg_cntl.c | 85 if (pg_cntl->ctx->dc->res_pool->dccg->funcs->enable_dsc && power_on) in pg_cntl35_dsc_pg_control()
86 pg_cntl->ctx->dc->res_pool->dccg->funcs->enable_dsc( in pg_cntl35_dsc_pg_control()
87 pg_cntl->ctx->dc->res_pool->dccg, dsc_inst); in pg_cntl35_dsc_pg_control()
148 if (pg_cntl->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on) { in pg_cntl35_dsc_pg_control()
150 pg_cntl->ctx->dc->res_pool->dccg->funcs->disable_dsc( in pg_cntl35_dsc_pg_control()
151 pg_cntl->ctx->dc->res_pool->dccg, dsc_inst); in pg_cntl35_dsc_pg_control()
411 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl35_plane_otg_pg_control()
443 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl35_plane_otg_pg_control()
486 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl35_init_pg_status()
496 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl35_init_pg_status()
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/hwss/dcn21/ |
| H A D | dcn21_hwseq.c | 83 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config); in dcn21_init_sys_ctx()
184 struct dmcu *dmcu = pipe_ctx->stream->ctx->dc->res_pool->dmcu; in dcn21_set_abm_immediate_disable()
217 struct dmcu *dmcu = pipe_ctx->stream->ctx->dc->res_pool->dmcu; in dcn21_set_pipe()
260 if (dc->dc->res_pool->dmcu) { in dcn21_set_backlight_level()
293 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn21_is_abm_supported()
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/link/protocols/ |
| H A D | link_edp_panel_control.c | 560 struct dmcu *dmcu = dc->res_pool->dmcu; in edp_set_psr_allow_active()
561 struct dmub_psr *psr = dc->res_pool->psr; in edp_set_psr_allow_active()
608 struct dmcu *dmcu = dc->res_pool->dmcu; in edp_get_psr_state()
609 struct dmub_psr *psr = dc->res_pool->psr; in edp_get_psr_state()
691 dmcu = dc->res_pool->dmcu; in edp_setup_psr()
692 psr = dc->res_pool->psr; in edp_setup_psr()
792 link->dc->res_pool->timing_generator_count; in edp_setup_psr()
867 struct dmub_psr *psr = dc->res_pool->psr; in edp_get_psr_residency()
882 struct dmub_psr *psr = dc->res_pool->psr; in edp_set_sink_vtotal_in_psr_active()
974 replay = dc->res_pool->replay; in edp_setup_replay()
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/link/ |
| H A D | link_factory.c | 394 link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = NULL; in link_destruct()
395 link->dc->res_pool->dig_link_enc_count--; in link_destruct()
498 if (link->dc->res_pool->funcs->link_init) in construct_phy()
499 link->dc->res_pool->funcs->link_init(link); in construct_phy()
612 link->dc->res_pool->funcs->link_enc_create(dc_ctx, &enc_init_data); in construct_phy()
626 link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = link->link_enc; in construct_phy()
627 link->dc->res_pool->dig_link_enc_count++; in construct_phy()
631 if (link->dc->res_pool->funcs->panel_cntl_create && in construct_phy()
638 link->dc->res_pool->funcs->panel_cntl_create( in construct_phy()
800 if (link->dc->res_pool->funcs->get_preferred_eng_id_dpia) in construct_dpia()
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