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/linux-6.15/sound/soc/ux500/
H A Dux500_msp_i2s.c294 msp->registers + MSP_MCR); in configure_multichannel()
296 msp->registers + MSP_TCE0); in configure_multichannel()
298 msp->registers + MSP_TCE1); in configure_multichannel()
300 msp->registers + MSP_TCE2); in configure_multichannel()
302 msp->registers + MSP_TCE3); in configure_multichannel()
315 msp->registers + MSP_MCR); in configure_multichannel()
334 msp->registers + MSP_MCR); in configure_multichannel()
495 msp->registers + MSP_IMSC); in disable_msp_rx()
511 msp->registers + MSP_IMSC); in disable_msp_tx()
527 msp->registers + MSP_GCR); in disable_msp()
[all …]
/linux-6.15/drivers/media/radio/si470x/
H A Dradio-si470x-common.c209 radio->registers[CHANNEL] &= ~CHANNEL_CHAN; in si470x_set_chan()
229 radio->registers[CHANNEL] &= ~CHANNEL_TUNE; in si470x_set_chan()
327 radio->registers[POWERCFG] |= POWERCFG_SEEK; in si470x_set_seek()
331 radio->registers[POWERCFG] |= POWERCFG_SKMODE; in si470x_set_seek()
333 radio->registers[POWERCFG] |= POWERCFG_SEEKUP; in si470x_set_seek()
354 radio->registers[POWERCFG] &= ~POWERCFG_SEEK; in si470x_set_seek()
372 radio->registers[POWERCFG] = in si470x_start()
390 radio->registers[SYSCONFIG2] = in si470x_start()
401 radio->registers[CHANNEL] & CHANNEL_CHAN); in si470x_start()
423 radio->registers[POWERCFG] &= ~POWERCFG_DMUTE; in si470x_stop()
[all …]
H A Dradio-si470x-i2c.c187 radio->registers[SYSCONFIG1] |= 0x1 << 2; in si470x_fops_open()
275 bler = (radio->registers[STATUSRSSI] & in si470x_i2c_interrupt()
277 rds = radio->registers[RDSA]; in si470x_i2c_interrupt()
280 bler = (radio->registers[READCHAN] & in si470x_i2c_interrupt()
282 rds = radio->registers[RDSB]; in si470x_i2c_interrupt()
285 bler = (radio->registers[READCHAN] & in si470x_i2c_interrupt()
287 rds = radio->registers[RDSC]; in si470x_i2c_interrupt()
290 bler = (radio->registers[READCHAN] & in si470x_i2c_interrupt()
292 rds = radio->registers[RDSD]; in si470x_i2c_interrupt()
396 radio->registers[POWERCFG] = POWERCFG_ENABLE; in si470x_i2c_probe()
[all …]
H A Dradio-si470x-usb.c388 radio->registers[STATUSRSSI] = in si470x_int_in_callback()
397 radio->registers[STATUSRSSI + regnr] = in si470x_int_in_callback()
412 bler = (radio->registers[STATUSRSSI] & in si470x_int_in_callback()
414 rds = radio->registers[RDSA]; in si470x_int_in_callback()
417 bler = (radio->registers[READCHAN] & in si470x_int_in_callback()
419 rds = radio->registers[RDSB]; in si470x_int_in_callback()
422 bler = (radio->registers[READCHAN] & in si470x_int_in_callback()
424 rds = radio->registers[RDSC]; in si470x_int_in_callback()
427 bler = (radio->registers[READCHAN] & in si470x_int_in_callback()
429 rds = radio->registers[RDSD]; in si470x_int_in_callback()
[all …]
/linux-6.15/drivers/scsi/smartpqi/
H A Dsmartpqi_sis.c116 &ctrl_info->registers->sis_mailbox[7])); in sis_wait_for_ctrl_ready_with_timeout()
161 readl(&ctrl_info->registers->sis_mailbox[7])); in sis_is_firmware_running()
185 struct pqi_ctrl_registers __iomem *registers; in sis_send_sync_cmd() local
191 registers = ctrl_info->registers; in sis_send_sync_cmd()
194 writel(cmd, &registers->sis_mailbox[0]); in sis_send_sync_cmd()
201 writel(params->mailbox[i], &registers->sis_mailbox[i]); in sis_send_sync_cmd()
205 &registers->sis_ctrl_to_host_doorbell_clear); in sis_send_sync_cmd()
208 writel(~0, &registers->sis_interrupt_mask); in sis_send_sync_cmd()
215 readl(&registers->sis_interrupt_mask); in sis_send_sync_cmd()
236 cmd_status = readl(&registers->sis_mailbox[0]); in sis_send_sync_cmd()
[all …]
/linux-6.15/Documentation/driver-api/media/drivers/ccs/
H A Dccs-regs.asc18 # general status registers
174 # analog gain registers
179 # digital gain registers
182 # hdr control registers
203 # clock set-up registers
221 # frame timing registers
225 # image size registers
233 # timing mode registers
243 # sub-sampling registers
391 # usl control registers
[all …]
/linux-6.15/Documentation/devicetree/bindings/pinctrl/
H A Dnxp,s32g2-siul2-pinctrl.yaml41 - description: MSCR registers group 0 in SIUL2_0
42 - description: MSCR registers group 1 in SIUL2_1
43 - description: MSCR registers group 2 in SIUL2_1
44 - description: IMCR registers group 0 in SIUL2_0
45 - description: IMCR registers group 1 in SIUL2_1
46 - description: IMCR registers group 2 in SIUL2_1
96 /* MSCR0-MSCR101 registers on siul2_0 */
98 /* MSCR112-MSCR122 registers on siul2_1 */
100 /* MSCR144-MSCR190 registers on siul2_1 */
102 /* IMCR0-IMCR83 registers on siul2_0 */
[all …]
/linux-6.15/Documentation/devicetree/bindings/display/msm/
H A Dgmu.yaml100 - description: Core GMU registers
101 - description: GMU PDC registers
102 - description: GMU PDC sequence registers
134 - description: Core GMU registers
136 - description: GMU PDC registers
171 - description: Core GMU registers
172 - description: GMU PDC registers
190 - description: Core GMU registers
192 - description: GMU PDC registers
238 - description: Core GMU registers
[all …]
/linux-6.15/drivers/gpio/
H A Dgpio-74x164.c25 u32 registers; member
33 u8 buffer[] __counted_by(registers);
39 chip->registers); in __gen_74x164_write_config()
45 u8 bank = chip->registers - 1 - offset / 8; in gen_74x164_get_value()
57 u8 bank = chip->registers - 1 - offset / 8; in gen_74x164_set_value()
81 for_each_set_clump8(offset, bankmask, mask, chip->registers * 8) { in gen_74x164_set_multiple()
82 bank = chip->registers - 1 - offset / 8; in gen_74x164_set_multiple()
135 chip->registers = nregs; in gen_74x164_probe()
147 chip->gpio_chip.ngpio = GEN_74X164_NUMBER_GPIOS * chip->registers; in gen_74x164_probe()
/linux-6.15/Documentation/devicetree/bindings/mailbox/
H A Dmicrochip,mpfs-mailbox.yaml19 - description: mailbox data registers
21 - description: mailbox control & data registers
22 - description: mailbox interrupt registers
25 - description: mailbox control registers
26 - description: mailbox interrupt registers
27 - description: mailbox data registers
/linux-6.15/drivers/char/agp/
H A Damd-k7-agp.c32 volatile u8 __iomem *registers; member
216 if (!amd_irongate_private.registers) { in amd_irongate_configure()
220 if (!amd_irongate_private.registers) in amd_irongate_configure()
226 readl(amd_irongate_private.registers+AMD_ATTBASE); /* PCI Posting. */ in amd_irongate_configure()
235 enable_reg = readw(amd_irongate_private.registers+AMD_GARTENABLE); in amd_irongate_configure()
237 writew(enable_reg, amd_irongate_private.registers+AMD_GARTENABLE); in amd_irongate_configure()
246 writel(1, amd_irongate_private.registers+AMD_TLBFLUSH); in amd_irongate_configure()
259 enable_reg = readw(amd_irongate_private.registers+AMD_GARTENABLE); in amd_irongate_cleanup()
261 writew(enable_reg, amd_irongate_private.registers+AMD_GARTENABLE); in amd_irongate_cleanup()
268 iounmap((void __iomem *) amd_irongate_private.registers); in amd_irongate_cleanup()
[all …]
H A Dsworks-agp.c39 volatile u8 __iomem *registers; member
240 writeb(1, serverworks_private.registers+SVWRKS_POSTFLUSH); in serverworks_tlbflush()
242 while (readb(serverworks_private.registers+SVWRKS_POSTFLUSH) == 1) { in serverworks_tlbflush()
251 writel(1, serverworks_private.registers+SVWRKS_DIRFLUSH); in serverworks_tlbflush()
253 while (readl(serverworks_private.registers+SVWRKS_DIRFLUSH) == 1) { in serverworks_tlbflush()
273 if (!serverworks_private.registers) { in serverworks_configure()
278 writeb(0xA, serverworks_private.registers+SVWRKS_GART_CACHE); in serverworks_configure()
284 cap_reg = readw(serverworks_private.registers+SVWRKS_COMMAND); in serverworks_configure()
287 writew(cap_reg, serverworks_private.registers+SVWRKS_COMMAND); in serverworks_configure()
288 readw(serverworks_private.registers+SVWRKS_COMMAND); in serverworks_configure()
[all …]
/linux-6.15/Documentation/devicetree/bindings/dma/
H A Dcirrus,ep9301-dma-m2p.yaml30 - description: m2p0 channel registers
31 - description: m2p1 channel registers
32 - description: m2p2 channel registers
33 - description: m2p3 channel registers
34 - description: m2p4 channel registers
35 - description: m2p5 channel registers
36 - description: m2p6 channel registers
37 - description: m2p7 channel registers
38 - description: m2p8 channel registers
39 - description: m2p9 channel registers
H A Dnvidia,tegra210-adma.yaml31 used for accessing the DMA channel registers. The 'global'
32 region describes the address space of the global DMA registers.
35 registers and the DMA channel registers.
87 - description: Full address space range of DMA registers.
100 - description: Full address space range of DMA registers.
104 - description: Channel Page address space range of DMA registers.
111 - description: Channel Page address space range of DMA registers.
112 - description: Global Page address space range of DMA registers.
/linux-6.15/drivers/hv/
H A Dmshv_common.c27 struct hv_register_assoc *registers) in hv_call_get_vp_registers() argument
51 input_page->names[i] = registers[i].name; in hv_call_get_vp_registers()
60 registers[i].value = output_page[i]; in hv_call_get_vp_registers()
62 registers += completed; in hv_call_get_vp_registers()
73 struct hv_register_assoc *registers) in hv_call_set_vp_registers() argument
93 memcpy(input_page->elements, registers, in hv_call_set_vp_registers()
102 registers += completed; in hv_call_set_vp_registers()
/linux-6.15/Documentation/devicetree/bindings/thermal/
H A Drcar-gen3-thermal.yaml73 - description: TSC0 registers
74 - description: TSC1 registers
75 - description: TSC2 registers
76 - description: TSC3 registers
77 - description: TSC4 registers
83 - description: TSC1 registers
84 - description: TSC2 registers
85 - description: TSC3 registers
86 - description: TSC4 registers
/linux-6.15/Documentation/devicetree/bindings/powerpc/nintendo/
H A Dwii.txt31 - reg : should contain the VI registers location and length
42 - reg : should contain the PI registers location and length
64 - reg : should contain the DSP registers location and length
76 - reg : should contain the SI registers location and length
87 - reg : should contain the AI registers location and length
97 - reg : should contain the EXI registers location and length
107 - reg : should contain the EHCI registers location and length
117 - reg : should contain the SDHCI registers location and length
126 - reg : should contain the IPC registers location and length
155 - reg : should contain the control registers location and length
[all …]
/linux-6.15/Documentation/devicetree/bindings/net/
H A Dthead,th1520-gmac.yaml27 - APB registers are used to configure clock frequency/clock enable/clock
29 - AHB registers are use to configure GMAC core (DesignWare Core part).
30 GMAC core register consists of DMA registers and GMAC registers.
53 - description: DesignWare GMAC IP core registers
54 - description: GMAC APB registers
64 - description: Peripheral registers interface clock
/linux-6.15/drivers/gpu/drm/msm/adreno/
H A Da6xx_gpu_state.c33 struct a6xx_gpu_state_obj *registers; member
1133 regs->registers[i] + j); in a6xx_get_ahb_gpu_registers()
1304 if (!a6xx_state->registers) in a6xx_get_registers()
1311 &a6xx_state->registers[index++]); in a6xx_get_registers()
1339 &a6xx_state->registers[index++], in a6xx_get_registers()
1390 if (!a6xx_state->registers) in a7xx_get_registers()
1689 u32 count = RANGE(registers, i); in a6xx_show_registers()
1690 u32 offset = registers[i]; in a6xx_show_registers()
1709 u32 count = RANGE(registers, i); in a7xx_show_registers_indented()
1710 u32 offset = registers[i]; in a7xx_show_registers_indented()
[all …]
/linux-6.15/Documentation/arch/sh/
H A Dregister-banks.rst17 In the case of this type of banking, banked registers are mapped directly to
19 can still be used to reference the banked registers (as r0_bank ... r7_bank)
21 in mind when writing code that utilizes these banked registers, for obvious
23 be used rather effectively as scratch registers by the kernel.
25 Presently the kernel uses several of these registers.
28 registers when doing exception handling).
/linux-6.15/Documentation/devicetree/bindings/timer/
H A Drealtek,otto-timer.yaml28 - description: timer0 registers
29 - description: timer1 registers
30 - description: timer2 registers
31 - description: timer3 registers
32 - description: timer4 registers
/linux-6.15/drivers/gpu/drm/msm/
H A DMakefile175 $(headergen-opts) --rnn $(src)/registers --xml $< c-defines > $@
177 $(obj)/generated/%.xml.h: $(src)/registers/adreno/%.xml \
178 $(src)/registers/adreno/adreno_common.xml \
179 $(src)/registers/adreno/adreno_pm4.xml \
180 $(src)/registers/freedreno_copyright.xml \
181 $(src)/registers/gen_header.py \
182 $(src)/registers/rules-fd.xsd \
186 $(obj)/generated/%.xml.h: $(src)/registers/display/%.xml \
187 $(src)/registers/freedreno_copyright.xml \
188 $(src)/registers/gen_header.py \
[all …]
/linux-6.15/Documentation/devicetree/bindings/arm/marvell/
H A Dcoherency-fabric.txt18 - reg: Should contain coherency fabric registers location and
22 fabric registers, second pair for the per-CPU fabric registers.
25 for the per-CPU fabric registers.
28 for the per-CPU fabric registers.
/linux-6.15/Documentation/devicetree/bindings/spmi/
H A Dqcom,spmi-pmic-arb.yaml30 - description: core registers
31 - description: interrupt controller registers
32 - description: configuration registers
34 - description: core registers
36 - description: rx-channel (called observer) per virtual slave registers
37 - description: interrupt controller registers
38 - description: configuration registers
/linux-6.15/drivers/media/platform/rockchip/rkisp1/
H A Drkisp1-debug.c67 static const struct rkisp1_debug_register registers[] = { in rkisp1_debug_dump_core_regs_show() local
83 return rkisp1_debug_dump_regs(rkisp1, m, 0, registers); in rkisp1_debug_dump_core_regs_show()
89 static const struct rkisp1_debug_register registers[] = { in rkisp1_debug_dump_isp_regs_show() local
103 return rkisp1_debug_dump_regs(rkisp1, m, 0, registers); in rkisp1_debug_dump_isp_regs_show()
109 static const struct rkisp1_debug_register registers[] = { in rkisp1_debug_dump_rsz_regs_show() local
124 return rkisp1_debug_dump_regs(rsz->rkisp1, m, rsz->regs_base, registers); in rkisp1_debug_dump_rsz_regs_show()
130 static const struct rkisp1_debug_register registers[] = { in rkisp1_debug_dump_mi_mp_show() local
142 return rkisp1_debug_dump_regs(rkisp1, m, 0, registers); in rkisp1_debug_dump_mi_mp_show()

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