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/linux-6.15/Documentation/devicetree/bindings/mfd/
H A Dmc13xxx.txt55 sw1a : regulator SW1A (register 24, bit 0)
56 sw1b : regulator SW1B (register 25, bit 0)
57 sw2a : regulator SW2A (register 26, bit 0)
58 sw2b : regulator SW2B (register 27, bit 0)
60 vaudio : regulator VAUDIO (register 32, bit 0)
61 viohi : regulator VIOHI (register 32, bit 3)
62 violo : regulator VIOLO (register 32, bit 6)
86 sw1 : regulator SW1 (register 24, bit 0)
87 sw2 : regulator SW2 (register 25, bit 0)
88 sw3 : regulator SW3 (register 26, bit 0)
[all …]
/linux-6.15/Documentation/devicetree/bindings/cache/
H A Dqcom,llcc.yaml80 - description: LLCC0 base register region
96 - description: LLCC0 base register region
97 - description: LLCC1 base register region
123 - description: LLCC0 base register region
140 - description: LLCC0 base register region
141 - description: LLCC1 base register region
142 - description: LLCC2 base register region
143 - description: LLCC3 base register region
144 - description: LLCC4 base register region
145 - description: LLCC5 base register region
[all …]
/linux-6.15/drivers/scsi/aic7xxx/
H A Daic79xx.reg114 register INTSTAT {
211 register CLRINT {
229 register ERROR {
245 register CLRERR {
261 register HCNTRL {
410 register INTCTL {
515 register HADDR {
547 register HCNT {
802 register OST {
1254 register LQIN {
[all …]
H A Daic7xxx.reg68 register SCSISEQ {
196 register SCSIID {
237 register STCNT {
300 register SSTAT0 {
474 register SELID {
657 register ACCUM {
691 register NONE {
698 register FLAGS {
724 register STACK {
736 register BCTL {
[all …]
/linux-6.15/Documentation/hwmon/
H A Ducd9200.rst62 in1_input Measured voltage. From READ_VIN register.
63 in1_min Minimum Voltage. From VIN_UV_WARN_LIMIT register.
64 in1_max Maximum voltage. From VIN_OV_WARN_LIMIT register.
67 register.
74 in[2-5]_input Measured voltage. From READ_VOUT register.
79 register.
88 curr1_input Measured current. From READ_IIN register.
91 curr[2-5]_input Measured current. From READ_IOUT register.
94 IOUT_UC_FAULT_LIMIT register.
96 register.
[all …]
H A Dmax8688.rst49 in1_input Measured voltage. From READ_VOUT register.
50 in1_min Minimum Voltage. From VOUT_UV_WARN_LIMIT register.
51 in1_max Maximum voltage. From VOUT_OV_WARN_LIMIT register.
52 in1_lcrit Critical minimum Voltage. VOUT_UV_FAULT_LIMIT register.
54 register.
65 curr1_input Measured current. From READ_IOUT register.
66 curr1_max Maximum current. From IOUT_OC_WARN_LIMIT register.
68 register.
74 temp1_input Measured temperature. From READ_TEMPERATURE_1 register.
75 temp1_max Maximum temperature. From OT_WARN_LIMIT register.
[all …]
H A Dpmbus.rst211 From MFR_VIN_MIN or MFR_VOUT_MIN register.
213 From MFR_VIN_MAX or MFR_VOUT_MAX register.
219 From IOUT_UC_FAULT_LIMIT register.
234 From MFR_IIN_MAX or MFR_IOUT_MAX register.
239 POUT_OP_WARN_LIMIT register.
241 From POUT_OP_FAULT_LIMIT register.
253 From READ_TEMPERATURE_X register.
257 From UT_FAULT_LIMIT register.
259 From OT_FAULT_LIMIT register.
273 From MFR_TAMBIENT_MIN register.
[all …]
H A Dtps40422.rst48 in[1-2]_input Measured voltage. From READ_VOUT register.
51 curr[1-2]_input Measured current. From READ_IOUT register.
53 curr1_max Maximum current. From IOUT_OC_WARN_LIMIT register.
55 register.
60 temp1_input Measured temperature. From READ_TEMPERATURE_2 register
62 temp1_max Maximum temperature. From OT_WARN_LIMIT register.
63 temp1_crit Critical high temperature. From OT_FAULT_LIMIT register.
70 temp2_input Measured temperature. From READ_TEMPERATURE_2 register
H A Dmax16064.rst49 in[1-4]_input Measured voltage. From READ_VOUT register.
50 in[1-4]_min Minimum Voltage. From VOUT_UV_WARN_LIMIT register.
51 in[1-4]_max Maximum voltage. From VOUT_OV_WARN_LIMIT register.
52 in[1-4]_lcrit Critical minimum Voltage. VOUT_UV_FAULT_LIMIT register.
54 register.
64 temp1_input Measured temperature. From READ_TEMPERATURE_1 register.
65 temp1_max Maximum temperature. From OT_WARN_LIMIT register.
66 temp1_crit Critical high temperature. From OT_FAULT_LIMIT register.
/linux-6.15/arch/mips/boot/dts/mti/
H A Dsead3.dts114 compatible = "register-bit-led";
120 compatible = "register-bit-led";
126 compatible = "register-bit-led";
132 compatible = "register-bit-led";
138 compatible = "register-bit-led";
144 compatible = "register-bit-led";
150 compatible = "register-bit-led";
156 compatible = "register-bit-led";
163 compatible = "register-bit-led";
169 compatible = "register-bit-led";
[all …]
/linux-6.15/Documentation/devicetree/bindings/power/reset/
H A Dsyscon-poweroff.yaml7 title: Generic SYSCON mapped register poweroff driver
13 This is a generic poweroff driver using syscon to map the poweroff register.
14 The poweroff is generally performed with a write to the poweroff register
15 defined by the register map pointed by syscon reference plus the offset
18 The SYSCON register map is normally retrieved from the parental dt-node. So
28 description: Update only the register bits defined by the mask (32 bit).
32 description: Offset in the register map for the poweroff register (in bytes).
38 Phandle to the register map node. This property is deprecated in favor of
43 description: The poweroff value written to the poweroff register (32 bit access).
H A Dsyscon-reboot.yaml7 title: Generic SYSCON mapped register reset driver
13 This is a generic reset driver using syscon to map the reset register.
14 The reset is generally performed with a write to the reset register
15 defined by the SYSCON register map base plus the offset with the value and
28 description: Update only the register bits defined by the mask (32 bit).
32 description: Offset in the register map for the reboot register (in bytes).
36 description: Base address and size for the reboot register.
42 Phandle to the register map node. This property is deprecated in favor of
47 description: The reset value written to the reboot register (32 bit access).
/linux-6.15/Documentation/devicetree/bindings/leds/
H A Dregister-bit-led.yaml4 $id: http://devicetree.org/schemas/leds/register-bit-led.yaml#
14 bits in a certain register can turn on/off a single LED. The register bit LEDs
29 const: register-bit-led
33 The register address and size
38 bit mask for the bit controlling this LED in the register
48 register offset to the register controlling this LED
70 compatible = "register-bit-led";
79 compatible = "register-bit-led";
87 compatible = "register-bit-led";
/linux-6.15/Documentation/devicetree/bindings/reset/
H A Dti-syscon-reset.txt7 sometimes a part of a larger register space region implementing various
8 functionalities. This register range is best represented as a syscon node to
10 register space.
30 - ti,reset-bits : Contains the reset control register information
34 register from the syscon register base
36 assert control register
38 register from the syscon register base
40 deassert control register
41 Cell #5 : offset of the reset status register
42 from the syscon register base
[all …]
/linux-6.15/Documentation/ABI/testing/
H A Dsysfs-bus-coresight-devices-etb1020 value stored in this register+1 (from ARM ETB-TRM).
27 2. The value is read directly from HW register RDP, 0x004.
33 Description: (Read) Shows the value held by the ETB status register. The value
34 is read directly from HW register STS, 0x00C.
40 Description: (Read) Shows the value held by the ETB RAM Read Pointer register
42 interface. The value is read directly from HW register RRP,
52 from HW register RWP, 0x018.
59 read directly from HW register TRG, 0x01C.
66 is read directly from HW register CTL, 0x020.
73 register. The value is read directly from HW register FFSR,
[all …]
H A Dsysfs-bus-coresight-devices-tmc15 The value is read directly from HW register RSZ, 0x004.
22 is read directly from HW register STS, 0x00C.
30 interface. The value is read directly from HW register RRP,
40 from HW register RWP, 0x018.
47 read directly from HW register TRG, 0x01C.
54 is read directly from HW register CTL, 0x020.
61 register. The value is read directly from HW register FFSR,
69 register. The value is read directly from HW register FFCR,
76 Description: (Read) Shows the value held by the TMC Mode register, which
78 The value is read directly from the MODE register, 0x028.
[all …]
/linux-6.15/Documentation/devicetree/bindings/phy/
H A Dti-phy.txt7 "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.
8 "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register
15 "ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on
17 "ti,control-phy-usb2-am437" - if it has power down register like USB2 PHY on
19 - reg : register ranges as listed in the reg-names property
35 - reg : Address and length of the register set for the device.
36 - reg-names: The names of the register addresses corresponding to the registers
56 CTRL_CORE_SMA_SW_0 register and register offset to the CTRL_CORE_SMA_SW_0
57 register that contains the SATA_PLL_SOFT_RESET bit. Only valid for sata_phy.
59 register offset to write the PCS delay value.
[all …]
/linux-6.15/Documentation/virt/kvm/arm/
H A Dvcpu-features.rst27 system. The ID register values may be VM-scoped in KVM, meaning that the
40 scheme for fields in ID register'. KVM does not allow ID register values that
44 It is **strongly recommended** that userspace modify the ID register values
45 before accessing the rest of the vCPU's CPU register state. KVM may use the
46 ID register values to control feature emulation. Interleaving ID register
47 modification with other system register accesses may lead to unpredictable
/linux-6.15/Documentation/devicetree/bindings/net/
H A Dmicrel.txt12 KSZ8001: register 0x1e, bits 15..14
13 KSZ8041: register 0x1e, bits 15..14
14 KSZ8021: register 0x1f, bits 5..4
15 KSZ8031: register 0x1f, bits 5..4
16 KSZ8051: register 0x1f, bits 5..4
17 KSZ8081: register 0x1f, bits 5..4
18 KSZ8091: register 0x1f, bits 5..4
19 LAN8814: register EP5.0, bit 6
/linux-6.15/Documentation/devicetree/bindings/display/
H A Dbrcm,bcm2711-hdmi.yaml22 - description: HDMI controller register range
23 - description: DVP register range
24 - description: HDMI PHY register range
25 - description: Rate Manager register range
26 - description: Packet RAM register range
27 - description: Metadata RAM register range
28 - description: CSC register range
29 - description: CEC register range
30 - description: HD register range
/linux-6.15/Documentation/devicetree/bindings/gpio/
H A Dgpio-mmio.yaml14 Some simple GPIO controllers may consist of a single data register or a pair
38 A list of registers in the controller. The width of each register is
46 This register may also be used to drive GPIOs if the SET register is
50 register will drive the GPIO line high.
53 register will drive the GPIO line low. If this register is omitted,
54 the SET register will be used to clear the GPIO lines as well, by
57 Register to set the line as OUTPUT. Setting a bit in this register
61 Register to set this line as INPUT. Setting a bit in this register
83 to the first 0 .. ngpios lines. This is useful when the GPIO MMIO register
/linux-6.15/Documentation/devicetree/bindings/mmc/
H A Dsdhci.txt7 - sdhci-caps-mask: The sdhci capabilities register is incorrect. This 64bit
8 property corresponds to the bits in the sdhci capability register. If the bit
9 is on in the mask then the bit is incorrect in the register and should be
11 - sdhci-caps: The sdhci capabilities register is incorrect. This 64bit
12 property corresponds to the bits in the sdhci capability register. If the
/linux-6.15/Documentation/devicetree/bindings/clock/ti/
H A Dti,mux-clock.yaml13 This clock assumes a register-mapped multiplexer with multiple inpt clock
18 as they are programmed into the register. E.g:
22 Results in programming the register as follows:
24 register value selected parent clock
30 into the register, instead indexing begins at 1. The optional property
33 register value selected clock parent
38 The binding must provide the register to control the mux. Optionally
39 the number of bits to shift the control field in the register can be
81 Latch the mux value to HW, only needed if the register
/linux-6.15/Documentation/devicetree/bindings/i2c/
H A Di2c-mux-reg.txt3 This binding describes an I2C bus multiplexer that uses a single register
14 - reg: this pair of <offset size> specifies the register to control the mux.
18 - little-endian: The existence indicates the register is in little endian.
19 - big-endian: The existence indicates the register is in big endian.
22 - write-only: The existence indicates the register is write-only.
27 in the relevant node's reg property will be output to the register.
31 register will be set according to the idle value.
34 left programmed into the register.
45 little-endian; /* little endian register on PCIe */
/linux-6.15/Documentation/PCI/endpoint/
H A Dpci-test-function.rst33 This register will be used to test BAR0. A known pattern will be written
34 and read back from MAGIC register to verify BAR0.
38 This register will be used by the host driver to indicate the function
54 This register reflects the status of the PCI endpoint device.
72 This register contains the source address (RC buffer address) for the
77 This register contains the destination address (RC buffer address) for
82 This register contains the interrupt type (Legacy/MSI) triggered
95 This register contains the triggered ID interrupt.

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