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Searched refs:regWD_UTCL1_STATUS (Results 1 – 9 of 9) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_2_offset.h3598 #define regWD_UTCL1_STATUS … macro
H A Dgc_9_4_3_offset.h308 #define regWD_UTCL1_STATUS … macro
H A Dgc_11_5_0_offset.h1163 #define regWD_UTCL1_STATUS … macro
H A Dgc_12_0_0_offset.h2220 #define regWD_UTCL1_STATUS … macro
H A Dgc_11_0_0_offset.h2066 #define regWD_UTCL1_STATUS … macro
H A Dgc_11_0_3_offset.h2128 #define regWD_UTCL1_STATUS … macro
/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_4_3.c90 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS),
H A Dgfx_v12_0.c122 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS),
H A Dgfx_v11_0.c167 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS),