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Searched refs:regVM_L2_PROTECTION_FAULT_CNTL (Results 1 – 8 of 8) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dgfxhub_v1_2.c492 tmp = RREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL); in gfxhub_v1_2_xcc_set_fault_enable_default()
523 WREG32_SOC15(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL, tmp); in gfxhub_v1_2_xcc_set_fault_enable_default()
568 SOC15_REG_OFFSET(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL); in gfxhub_v1_2_xcc_init()
H A Dmmhub_v1_8.c506 tmp = RREG32_SOC15(MMHUB, i, regVM_L2_PROTECTION_FAULT_CNTL); in mmhub_v1_8_set_fault_enable_default()
537 WREG32_SOC15(MMHUB, i, regVM_L2_PROTECTION_FAULT_CNTL, tmp); in mmhub_v1_8_set_fault_enable_default()
564 regVM_L2_PROTECTION_FAULT_CNTL); in mmhub_v1_8_init()
H A Dmmhub_v1_7.c416 tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL); in mmhub_v1_7_set_fault_enable_default()
448 WREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL, tmp); in mmhub_v1_7_set_fault_enable_default()
470 SOC15_REG_OFFSET(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL); in mmhub_v1_7_init()
H A Dgfx_v9_4_3.c91 SOC15_REG_ENTRY_STR(GC, 0, regVM_L2_PROTECTION_FAULT_CNTL),
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/mmhub/
H A Dmmhub_1_8_0_offset.h2588 #define regVM_L2_PROTECTION_FAULT_CNTL … macro
H A Dmmhub_1_7_offset.h4438 #define regVM_L2_PROTECTION_FAULT_CNTL … macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_2_offset.h6704 #define regVM_L2_PROTECTION_FAULT_CNTL … macro
H A Dgc_9_4_3_offset.h1498 #define regVM_L2_PROTECTION_FAULT_CNTL … macro