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Searched refs:regUVD_STATUS (Results 1 – 10 of 10) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v5_0_0.c42 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS),
311 RREG32_SOC15(VCN, i, regUVD_STATUS))) { in vcn_v5_0_0_hw_fini()
831 tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY; in vcn_v5_0_0_start()
832 WREG32_SOC15(VCN, i, regUVD_STATUS, tmp); in vcn_v5_0_0_start()
877 status = RREG32_SOC15(VCN, i, regUVD_STATUS); in vcn_v5_0_0_start()
921 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0, in vcn_v5_0_0_start()
1011 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v5_0_0_stop()
1056 WREG32_SOC15(VCN, i, regUVD_STATUS, 0); in vcn_v5_0_0_stop()
1240 ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v5_0_0_is_idle()
1262 ret = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, in vcn_v5_0_0_wait_for_idle()
[all …]
H A Dvcn_v5_0_1.c690 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS) | UVD_STATUS__UVD_BUSY; in vcn_v5_0_1_start()
691 WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, tmp); in vcn_v5_0_1_start()
736 status = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS); in vcn_v5_0_1_start()
780 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_STATUS), 0, in vcn_v5_0_1_start()
874 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v5_0_1_stop()
919 WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, 0); in vcn_v5_0_1_stop()
1046 ret &= (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v5_0_1_is_idle()
1064 ret = SOC15_WAIT_ON_RREG(VCN, GET_INST(VCN, i), regUVD_STATUS, UVD_STATUS__IDLE, in vcn_v5_0_1_wait_for_idle()
1092 if (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) != UVD_STATUS__IDLE) in vcn_v5_0_1_set_clockgating_state()
H A Dvcn_v4_0_5.c58 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS),
333 RREG32_SOC15(VCN, i, regUVD_STATUS))) { in vcn_v4_0_5_hw_fini()
1065 tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY; in vcn_v4_0_5_start()
1066 WREG32_SOC15(VCN, i, regUVD_STATUS, tmp); in vcn_v4_0_5_start()
1140 status = RREG32_SOC15(VCN, i, regUVD_STATUS); in vcn_v4_0_5_start()
1184 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0, in vcn_v4_0_5_start()
1276 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v4_0_5_stop()
1321 WREG32_SOC15(VCN, i, regUVD_STATUS, 0); in vcn_v4_0_5_stop()
1515 ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v4_0_5_is_idle()
1537 ret = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, in vcn_v4_0_5_wait_for_idle()
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H A Dvcn_v4_0_3.c52 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS),
1017 MMSCH_V4_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, 0, regUVD_STATUS), in vcn_v4_0_3_start_sriov()
1179 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS) | in vcn_v4_0_3_start()
1181 WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, tmp); in vcn_v4_0_3_start()
1259 regUVD_STATUS); in vcn_v4_0_3_start()
1294 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_STATUS), 0, in vcn_v4_0_3_start()
1388 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_STATUS, in vcn_v4_0_3_stop()
1437 WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, 0); in vcn_v4_0_3_stop()
1630 ret &= (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) == in vcn_v4_0_3_is_idle()
1650 ret = SOC15_WAIT_ON_RREG(VCN, GET_INST(VCN, i), regUVD_STATUS, in vcn_v4_0_3_wait_for_idle()
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H A Dvcn_v4_0.c58 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS),
392 RREG32_SOC15(VCN, i, regUVD_STATUS))) { in vcn_v4_0_hw_fini()
1160 tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY; in vcn_v4_0_start()
1161 WREG32_SOC15(VCN, i, regUVD_STATUS, tmp); in vcn_v4_0_start()
1235 status = RREG32_SOC15(VCN, i, regUVD_STATUS); in vcn_v4_0_start()
1278 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0, in vcn_v4_0_start()
1382 regUVD_STATUS), in vcn_v4_0_start_sriov()
1661 WREG32_SOC15(VCN, i, regUVD_STATUS, 0); in vcn_v4_0_stop()
2021 ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v4_0_is_idle()
2043 ret = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, in vcn_v4_0_wait_for_idle()
[all …]
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_6_0_offset.h1228 #define regUVD_STATUS … macro
H A Dvcn_5_0_0_offset.h330 #define regUVD_STATUS … macro
H A Dvcn_4_0_5_offset.h337 #define regUVD_STATUS … macro
H A Dvcn_4_0_0_offset.h350 #define regUVD_STATUS … macro
H A Dvcn_4_0_3_offset.h352 #define regUVD_STATUS … macro