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Searched refs:regUVD_RB_SIZE (Results 1 – 10 of 10) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v5_0_0.c64 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE),
775 WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE, ring->ring_size / 4); in vcn_v5_0_0_start_dpg_mode()
931 WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring->ring_size / 4); in vcn_v5_0_0_start()
H A Dvcn_v4_0_5.c80 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE),
1004 WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE, ring->ring_size / 4); in vcn_v4_0_5_start_dpg_mode()
1194 WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring->ring_size / 4); in vcn_v4_0_5_start()
H A Dvcn_v5_0_1.c639 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE, ring->ring_size / sizeof(uint32_t)); in vcn_v5_0_1_start_dpg_mode()
794 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE, ring->ring_size / 4); in vcn_v5_0_1_start()
H A Dvcn_v4_0_3.c74 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE),
944 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE, in vcn_v4_0_3_start_dpg_mode()
1306 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE, in vcn_v4_0_3_start()
H A Dvcn_v4_0.c80 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE),
1103 WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE, ring->ring_size / 4); in vcn_v4_0_start_dpg_mode()
1288 WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring->ring_size / 4); in vcn_v4_0_start()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_6_0_offset.h1316 #define regUVD_RB_SIZE … macro
H A Dvcn_5_0_0_offset.h188 #define regUVD_RB_SIZE … macro
H A Dvcn_4_0_5_offset.h197 #define regUVD_RB_SIZE … macro
H A Dvcn_4_0_0_offset.h210 #define regUVD_RB_SIZE … macro
H A Dvcn_4_0_3_offset.h210 #define regUVD_RB_SIZE … macro