Home
last modified time | relevance | path

Searched refs:regUVD_RB_BASE_LO (Results 1 – 10 of 10) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v5_0_0.c49 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO),
773 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v5_0_0_start_dpg_mode()
929 WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v5_0_0_start()
H A Dvcn_v4_0_5.c65 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO),
1002 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v4_0_5_start_dpg_mode()
1192 WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v4_0_5_start()
H A Dvcn_v5_0_1.c637 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO, lower_32_bits(ring->gpu_addr)); in vcn_v5_0_1_start_dpg_mode()
792 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v5_0_1_start()
H A Dvcn_v4_0_3.c59 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO),
939 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO, in vcn_v4_0_3_start_dpg_mode()
1301 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO, in vcn_v4_0_3_start()
H A Dvcn_v4_0.c65 SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO),
1101 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v4_0_start_dpg_mode()
1286 WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v4_0_start()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_6_0_offset.h1312 #define regUVD_RB_BASE_LO … macro
H A Dvcn_5_0_0_offset.h184 #define regUVD_RB_BASE_LO … macro
H A Dvcn_4_0_5_offset.h193 #define regUVD_RB_BASE_LO … macro
H A Dvcn_4_0_0_offset.h206 #define regUVD_RB_BASE_LO … macro
H A Dvcn_4_0_3_offset.h206 #define regUVD_RB_BASE_LO … macro