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Searched refs:regUVD_MASTINT_EN (Results 1 – 10 of 10) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v5_0_1.c598 VCN, 0, regUVD_MASTINT_EN), 0, 0, indirect); in vcn_v5_0_1_start_dpg_mode()
626 VCN, 0, regUVD_MASTINT_EN), in vcn_v5_0_1_start_dpg_mode()
698 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 0, in vcn_v5_0_1_start()
775 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), in vcn_v5_0_1_start()
H A Dvcn_v5_0_0.c737 VCN, inst_idx, regUVD_MASTINT_EN), 0, 0, indirect); in vcn_v5_0_0_start_dpg_mode()
765 VCN, inst_idx, regUVD_MASTINT_EN), in vcn_v5_0_0_start_dpg_mode()
839 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0, in vcn_v5_0_0_start()
916 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), in vcn_v5_0_0_start()
H A Dvcn_v4_0_5.c942 VCN, inst_idx, regUVD_MASTINT_EN), 0, 0, indirect); in vcn_v4_0_5_start_dpg_mode()
994 VCN, inst_idx, regUVD_MASTINT_EN), in vcn_v4_0_5_start_dpg_mode()
1076 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0, in vcn_v4_0_5_start()
1179 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), in vcn_v4_0_5_start()
H A Dvcn_v4_0_3.c876 VCN, 0, regUVD_MASTINT_EN), 0, 0, indirect); in vcn_v4_0_3_start_dpg_mode()
930 VCN, 0, regUVD_MASTINT_EN), in vcn_v4_0_3_start_dpg_mode()
1192 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 0, in vcn_v4_0_3_start()
1289 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), in vcn_v4_0_3_start()
H A Dvcn_v4_0.c1038 VCN, inst_idx, regUVD_MASTINT_EN), 0, 0, indirect); in vcn_v4_0_start_dpg_mode()
1092 VCN, inst_idx, regUVD_MASTINT_EN), in vcn_v4_0_start_dpg_mode()
1171 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0, in vcn_v4_0_start()
1273 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), in vcn_v4_0_start()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_6_0_offset.h1294 #define regUVD_MASTINT_EN … macro
H A Dvcn_5_0_0_offset.h166 #define regUVD_MASTINT_EN … macro
H A Dvcn_4_0_5_offset.h175 #define regUVD_MASTINT_EN … macro
H A Dvcn_4_0_0_offset.h188 #define regUVD_MASTINT_EN … macro
H A Dvcn_4_0_3_offset.h188 #define regUVD_MASTINT_EN … macro