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Searched refs:regSQ_CMD (Results 1 – 11 of 11) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_amdkfd_gfx_v12.c172 WREG32(SOC15_REG_OFFSET(GC, 0, regSQ_CMD), sq_cmd); in wave_control_execute_v12()
H A Damdgpu_amdkfd_gfx_v11.c583 WREG32(SOC15_REG_OFFSET(GC, 0, regSQ_CMD), sq_cmd); in wave_control_execute_v11()
H A Dgfx_v9_4_3.c3013 WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regSQ_CMD, value); in gfx_v9_4_3_ring_soft_recovery()
H A Dgfx_v12_0.c4620 WREG32_SOC15(GC, 0, regSQ_CMD, value); in gfx_v12_0_ring_soft_recovery()
H A Dgfx_v11_0.c6158 WREG32_SOC15(GC, 0, regSQ_CMD, value); in gfx_v11_0_ring_soft_recovery()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_2_offset.h6192 #define regSQ_CMD … macro
H A Dgc_9_4_3_offset.h502 #define regSQ_CMD … macro
H A Dgc_11_5_0_offset.h1261 #define regSQ_CMD … macro
H A Dgc_12_0_0_offset.h7315 #define regSQ_CMD … macro
H A Dgc_11_0_0_offset.h2170 #define regSQ_CMD … macro
H A Dgc_11_0_3_offset.h2236 #define regSQ_CMD … macro