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Searched refs:regSMU_PCIE_FENCED1_REG_BASE_IDX (Results 1 – 2 of 2) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/pcie/
H A Dpcie_6_1_0_offset.h625 #define regSMU_PCIE_FENCED1_REG_BASE_IDX … macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/nbio/
H A Dnbio_4_3_0_offset.h6869 #define regSMU_PCIE_FENCED1_REG_BASE_IDX … macro