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Searched refs:regSDMA0_STATUS_REG (Results 1 – 9 of 9) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v7_0.c61 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS_REG),
763 sdma_v7_0_get_reg_offset(adev, i, regSDMA0_STATUS_REG)); in sdma_v7_0_load_microcode()
1439 u32 tmp = RREG32(sdma_v7_0_get_reg_offset(adev, i, regSDMA0_STATUS_REG)); in sdma_v7_0_is_idle()
1455 sdma0 = RREG32(sdma_v7_0_get_reg_offset(adev, 0, regSDMA0_STATUS_REG)); in sdma_v7_0_wait_for_idle()
1456 sdma1 = RREG32(sdma_v7_0_get_reg_offset(adev, 1, regSDMA0_STATUS_REG)); in sdma_v7_0_wait_for_idle()
H A Dsdma_v6_0.c62 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS_REG),
1438 u32 tmp = RREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_STATUS_REG)); in sdma_v6_0_is_idle()
1454 sdma0 = RREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_STATUS_REG)); in sdma_v6_0_wait_for_idle()
1455 sdma1 = RREG32(sdma_v6_0_get_reg_offset(adev, 1, regSDMA0_STATUS_REG)); in sdma_v6_0_wait_for_idle()
H A Dsoc24.c120 { SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_STATUS_REG)},
H A Dsoc21.c257 { SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_STATUS_REG)},
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/sdma/
H A Dsdma_4_4_0_offset.h59 #define regSDMA0_STATUS_REG … macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_11_5_0_offset.h60 #define regSDMA0_STATUS_REG … macro
H A Dgc_12_0_0_offset.h56 #define regSDMA0_STATUS_REG … macro
H A Dgc_11_0_0_offset.h58 #define regSDMA0_STATUS_REG … macro
H A Dgc_11_0_3_offset.h58 #define regSDMA0_STATUS_REG … macro