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Searched refs:regSDMA0_RLC_CGCG_CTRL (Results 1 – 6 of 6) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v11_0.c5306 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); in gfx_v11_0_update_coarse_grain_clock_gating()
5308 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); in gfx_v11_0_update_coarse_grain_clock_gating()
5340 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); in gfx_v11_0_update_coarse_grain_clock_gating()
5342 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); in gfx_v11_0_update_coarse_grain_clock_gating()
H A Dgfx_v12_0.c3950 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL); in gfx_v12_0_update_coarse_grain_clock_gating()
3952 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data); in gfx_v12_0_update_coarse_grain_clock_gating()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_11_5_0_offset.h152 #define regSDMA0_RLC_CGCG_CTRL … macro
H A Dgc_12_0_0_offset.h140 #define regSDMA0_RLC_CGCG_CTRL … macro
H A Dgc_11_0_0_offset.h150 #define regSDMA0_RLC_CGCG_CTRL … macro
H A Dgc_11_0_3_offset.h150 #define regSDMA0_RLC_CGCG_CTRL … macro