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Searched refs:regRLC_SPM_MC_CNTL (Results 1 – 9 of 9) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v12_0.c3799 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); in gfx_v12_0_update_spm_vmid()
3809 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); in gfx_v12_0_update_spm_vmid()
3811 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data); in gfx_v12_0_update_spm_vmid()
3817 uint32_t reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); in gfx_v12_0_update_spm_vmid()
H A Dgfx_v9_4_3.c1626 reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL); in gfx_v9_4_3_update_spm_vmid()
1637 WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); in gfx_v9_4_3_update_spm_vmid()
1639 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); in gfx_v9_4_3_update_spm_vmid()
H A Dgfx_v11_0.c5386 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); in gfx_v11_0_update_spm_vmid()
5397 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); in gfx_v11_0_update_spm_vmid()
5399 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data); in gfx_v11_0_update_spm_vmid()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_2_offset.h5046 #define regRLC_SPM_MC_CNTL … macro
H A Dgc_9_4_3_offset.h6560 #define regRLC_SPM_MC_CNTL … macro
H A Dgc_11_5_0_offset.h9009 #define regRLC_SPM_MC_CNTL … macro
H A Dgc_12_0_0_offset.h7019 #define regRLC_SPM_MC_CNTL … macro
H A Dgc_11_0_0_offset.h10578 #define regRLC_SPM_MC_CNTL … macro
H A Dgc_11_0_3_offset.h11198 #define regRLC_SPM_MC_CNTL … macro