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Searched refs:regRLC_PG_CNTL (Results 1 – 8 of 8) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v11_0.c2186 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); in gfx_v11_0_rlc_smu_handshake_cntl()
2200 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl); in gfx_v11_0_rlc_smu_handshake_cntl()
2389 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0); in gfx_v11_0_rlc_resume()
5428 u32 data = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); in gfx_v11_cntl_power_gating()
5435 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, data); in gfx_v11_cntl_power_gating()
H A Dgfx_v12_0.c1858 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL); in gfx_v12_0_rlc_smu_handshake_cntl()
1872 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl); in gfx_v12_0_rlc_smu_handshake_cntl()
2011 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0); in gfx_v12_0_rlc_resume()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_2_offset.h4968 #define regRLC_PG_CNTL … macro
H A Dgc_9_4_3_offset.h6480 #define regRLC_PG_CNTL … macro
H A Dgc_11_5_0_offset.h8559 #define regRLC_PG_CNTL … macro
H A Dgc_12_0_0_offset.h6390 #define regRLC_PG_CNTL … macro
H A Dgc_11_0_0_offset.h9888 #define regRLC_PG_CNTL … macro
H A Dgc_11_0_3_offset.h10490 #define regRLC_PG_CNTL … macro