Home
last modified time | relevance | path

Searched refs:regRLC_CNTL (Results 1 – 9 of 9) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v12_0.c1296 WREG32_SOC15(GC, 0, regRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); in gfx_v12_0_rlc_backdoor_autoload_enable()
1839 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL); in gfx_v12_0_rlc_stop()
1842 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp); in gfx_v12_0_rlc_stop()
3744 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL); in gfx_v12_0_is_rlc_enabled()
H A Dgfx_v11_0.c2167 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL); in gfx_v11_0_rlc_stop()
2170 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp); in gfx_v11_0_rlc_stop()
5105 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL); in gfx_v11_0_is_rlc_enabled()
H A Dgfx_v9_4_3.c1354 rlc_setting = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CNTL); in gfx_v9_4_3_is_rlc_enabled()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_2_offset.h4888 #define regRLC_CNTL … macro
H A Dgc_9_4_3_offset.h6392 #define regRLC_CNTL … macro
H A Dgc_11_5_0_offset.h8471 #define regRLC_CNTL … macro
H A Dgc_12_0_0_offset.h6298 #define regRLC_CNTL … macro
H A Dgc_11_0_0_offset.h9800 #define regRLC_CNTL … macro
H A Dgc_11_0_3_offset.h10402 #define regRLC_CNTL … macro